| PART |
Description |
Maker |
| UPD44325084 UPD44325084F5-E50-EQ2 UPD44325094F5-E5 |
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, RG142B/U COAX, DOUBLE SHIELDED
36M-BIT QDRII SRAM 4-WORD BURST OPERATION 36M条位推出QDRII SRAM4个字爆发运作
36M-BIT QDRII SRAM 4-WORD BURST OPERATION 36M条位推出QDRII SRAM个字爆发运作
4M X 8 QDR SRAM, 0.45 ns, PBGA165 13 X 15 MM, PLASTIC, FBGA-165
|
NEC Corp.
NEC, Corp.
|
| UPD44164364F5-E60-EQ1 UPD44164084 UPD44164084F5-E4 |
18M-BIT DDRII SRAM 4-WORD BURST OPERATION
|
NEC[NEC]
|
| PD46184185BF1-E40-EQ1 PD46184095BF1-E40-EQ1 PD4618 |
18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
|
Renesas Electronics Corporation
|
| CY7C1314BV18-167BZXC |
18-Mbit QDRII SRAM 2 Word Burst Architecture 512K X 36 QDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1263V18-300BZI |
36-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 18 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1411AV18-200BZI CY7C1411AV18-250BZI CY7C1411AV |
36-Mbit QDRII SRAM 4-Word Burst Architecture 2M X 18 QDR SRAM, 0.45 ns, PBGA165
36-Mbit QDRII SRAM 4-Word Burst Architecture 1M X 36 QDR SRAM, 0.45 ns, PBGA165
36-Mbit QDRII SRAM 4-Word Burst Architecture 2M X 18 QDR SRAM, 0.5 ns, PBGA165
36-Mbit QDRII SRAM 4-Word Burst Architecture 4M X 8 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1543V18-300BZI CY7C1545V18-375BZI |
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 QDR SRAM, 0.45 ns, PBGA165
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 2M X 36 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CYPT1542AV18-250GCMB CYPT1544AV18-250GCMB CYRS1542 |
72-Mbit QDRII SRAM Two-Word Burst Architecture with RadStop™ Technology
|
Cypress
|
| CYPT1543AV18-250GCMB CYPT1545AV18-250GCMB CYRS1543 |
72-Mbit QDRII SRAM Four-Word Burst Architecture with RadStop™ Technology
|
Cypress
|
| CY7C1241V18 CY7C1243V18 CY7C1241V18-300BZC CY7C124 |
36-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的国防评估报告⑩- II SRAM4字突发架构（2.0周期读写延迟
|
Cypress Semiconductor Corp.
|
