| PART |
Description |
Maker |
| 74V1T80CTR 74V1T80STR |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
ST Microelectronics
|
| 74V1T79STR 74V1T79 74V1T79CTR |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
|
| 74V1T80STR 74V1T80 74V1T80CTR |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| 74V1G79STR 74V1G79 74V1G79CTR |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
意法半导
|
| 74V1G80STR 74V1G80 74V1G80CTR |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| HD74ALVC1G80 |
From old datasheet system
Single Positive Edge-triggered D-type Flip Flop
|
HITACHI[Hitachi Semiconductor]
|
| 74AUP1G374GS |
Low-power D-type flip-flop; positive-edge trigger; 3-state AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6
|
NXP Semiconductors N.V.
|
| 74AUP1G74GT-G 74AUP1G74GF |
Low-power D-type flip-flop with set and reset; positive-edge trigger AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| 74F109_00 74F109 74F109PC 74F109SC 74F109SJ 74F109 |
From old datasheet system
Dual JK Positive Edge-Triggered Flip-Flop
Dual JK# Positive Edge-Triggered Flip-Flop
|
FAIRCHILD[Fairchild Semiconductor]
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| 74AUP2G79GF 74AUP2G79GS |
Low-power dual D-type flip-flop; positive-edge trigger AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
