| PART |
Description |
Maker |
| CD4027BMS FN3302 CD4027 |
J-K Flop Flop, Master-Slave, Dual, Rad-Hard, CMOS, Logic
CMOS Dual J-K Master-Slave Flip-Flop
From old datasheet system
|
INTERSIL[Intersil Corporation]
|
| MC10H135-D |
Dual J-K Master Slave Flip-Flop
|
ON Semiconductor
|
| DM7476N |
Dual Master-Slave J-K Flip-Flops with Clear/ Preset/ and Complementary Outputs
Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| DM74LS73A DM74LS73AN 74LS73 74LS73A DM74LS73AM |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
|
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| MC10H131FNR2G MC10H131MELG MC10H131FNG |
Dual D Type Master−Slave Flip−Flop 10H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20
Dual D Type Master−Slave Flip−Flop 10H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
ON Semiconductor
|
| 57401AJ/883B C57401AJ/883B 57401J 57401L 57402J 57 |
DUAL 'D' - TYPE FLIP-FLOP
x5 Asynchronous FIFO
7 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS
QUAD BILATERAL SWITCH
DUAL-J-K MASTER-SLAVE FLIP-FLOP X5的异步FIFO
x4 Asynchronous FIFO x4异步FIFO
|
Atmel, Corp.
NIC Components, Corp.
|
| CD4096B |
Inverting Gated JK Master Slave Flip Flop
|
ETC
|
| MC1018602 MC10186FN MC10186L MC10186P MC10186 MC10 |
Hex D Master-Slave Flip-Flop with Reset
|
ONSEMI[ON Semiconductor]
|
| MC10H176 MC10H176FN MC10H176L MC10H176P ON0771 |
From old datasheet system
Hex D Master-Slave Flip-Flop
|
ONSEMI[ON Semiconductor]
Motorola, Inc
|
| MC10186 MC10186FN MC10186L MC10186P ON0596 |
From old datasheet system
PIN ASSIGNMENT
Hex D Master-Slave Flip-Flop With Reset
|
ONSEMI[ON Semiconductor]
MOTOROLA[Motorola Inc]
Motorola, Inc
|
| CD4096BMS CD4095BMS FN3331 CDB4096BMS CD4096BMSFN3 |
Radiation Hardened CMOS Gated J-K Master-Slave Flip-Flops
From old datasheet system
|
Intersil Corporation
|
| DFF2 |
DFF2 is a fast , static, master-slave D flip-flop with 2x drive strngth. SET and RESET are asynchronous and active low
|
austriamicrosystems AG
|
