| PART |
Description |
Maker |
| EP2SGX60C EP2SGX30CF780C5N EP2SGX30D EP2SGX60CF780 |
Section I. Stratix II GX Device Data Sheet
Support for numerous single-ended and differential I/O standards
Section I. Stratix II GX Device Data Sheet
|
Altera Corporation
|
| 53261-0890 53261-0690 |
1.25 W-TO-B CONN. 51021,53261 MATING CROSS SECTION
1.25 W-TO-B CONN. MATING CROSS SECTION
|
Molex Electronics Ltd.
|
| M5LV-256_104-10VC M5LV-256_104-10VI M5LV-256_104-1 |
7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
20ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
10ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
12ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
15ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
|
LATTICE[Lattice Semiconductor]
|
| CY7C1302DV25-167BZC CY7C1302DV25-167BZI CY7C1302DV |
9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR垄芒 Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture
|
Cypress Semiconductor
|
| CY7C1518JV18-250BZC CY7C1518JV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CAT52045 |
Attenuator 5 Section
|
DAICO[DAICO Industries, Inc.]
|
| DAO944-10 |
GaAs 1 Section Attenuator
|
DAICO[DAICO Industries, Inc.]
|
| DA0984-1 |
GaAs 4 Section Attenuator
|
DAICO[DAICO Industries, Inc.]
|
| DA0996 |
GaAs 6 Section Attenuator
|
DAICO[DAICO Industries, Inc.]
|
