| PART |
Description |
Maker |
| AH291-P AH291-PA AH291-PL AH291-PLA AH291-YLA AH29 |
V(cc): 8V; I(peak): 500mA; 550-800mW; low voltage hall-effect smart fan motor controller
|
Anachip
|
| PU150-10 |
Switching power supply, 150W. Output #1: Vnom 5V, Imin 0A, Imax 30A, Ipeak 35A.
|
IPiQ
|
| NX8562LB NX8562LB-BA NX8562LB-CA NX8563LB NDL7603P |
1 550 nm CW LIGHT SOURCE InGaAsP STRAINED MQW-DFB LASER DIODE MODULE 1 550 nm的连续光源InGaAsP的应变量子阱激光器激光二极管模块
|
NEC, Corp.
NEC Corp.
NEC[NEC]
|
| PS9617 PS9617L-V-E4-A PS9617-A PS9617L PS9617L-A P |
GIGATRUE 550 CAT PATCH CABLE NO BOOT 7FT BLACK 高噪音减少，高速数字输出型8引脚DIP光耦合
GIGATRUE 550 CAT PATCH CBL NO BOOT 1FT BK 25 PK 高噪音减少，高速数字输出型8引脚DIP光耦合
HIGH NOISE REDUCTION, HIGH SPEED DIGITAL OUTPUT TYPE 8-PIN DIP PHOTOCOUPLER 高噪音减少，高速数字输出型8引脚DIP光耦合
GIGATRUE 550 CAT6 PATCH 2 FT, NON BOOT, BLACK
GIGATRUE 550 CAT PATCH CABLE NO BOOT 3FT BLACK
GIGATRUE 550 CAT PATCH CBL NO BOOT 100F PK 25 PK
GIGATRUE 550 CAT PATCH CABLE NO BOOT 7FT BLACK
|
Electronic Theatre Controls, Inc.
List of Unclassifed Manufacturers
ETC[ETC]
|
| S6B0717X01-B0CZ S6B0717X01-B0CY S6B0717X01-XXX0 S6 |
GIGATRUE 550 CAT6 ORANGE STRANDED BULK 500FT
GIGATRUE 550 CAT6 ORANGE STRANDED BULK 250FT
CAT5 SHLD, PVC PATCH CBL STRGHT PIN, 100MHZ-YELLOW
GIGATRUE 550 CAT6 ORANGE STRANDED BULK 1000FT
55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
|
SAMSUNG SEMICONDUCTOR CO. LTD.
|
| AT17N002 AT17N010 AT17N040 AT17N256 AT17N512 AT17N |
COVER 256K X 1 CONFIGURATION MEMORY, PDSO20
FPGA Configuration Memory 256K X 1 CONFIGURATION MEMORY, PDSO20
CAT5 SHLD, PVC PATCH CBL STRGHT PIN, 100 MHZ-GREEN 1M X 1 CONFIGURATION MEMORY, PDIP8
GIGATRUE 550 CAT6 PATCH 100 FT, NON BOOT, ORANGE
GIGATRUE 550 CAT6 PATCH 25 FT, NON BOOT, ORANGE
GIGATRUE 550 CAT6 PATCH 50 FT, NON BOOT, ORANGE
GIGATRUE 550 CAT6 PATCH 15 FT, NON BOOT, ORANGE
GIGATRUE 550 CAT6 PATCH 10 FT, NON BOOT, ORANGE
GIGATRUE 550 CAT6 PATCH 30 FT, NON BOOT, ORANGE
GIGATRUE 550 CAT6 PATCH 20 FT, NON BOOT, ORANGE
AT17N/256/512/010/002/040 [Updated 5/03. 18 Pages]
512K-bit FPGA Configuration EEPROM 3.3V
256K-bit FPGA Configuration EEPROM 3.3V
4M-bit FPGA Configuration EEPROM 3.3V
1M-bit FPGA Configuration EEPROM 3.3V
2M-bit FPGA Configuration EEPROM 3.3V
|
Atmel, Corp.
聚兴科技股份有限公司
Atmel Corp.
|
| APL5551KI-TR APL5551 APL5551KAI-TR APL5551KAI-TRL |
Dual Channel 500mA/500mA Regulator Reset IC
|
ANPEC[Anpec Electronics Coropration]
|
| MAX1857 MAX1857EUA47 |
Replaced by TMS320C6202B : Fixed-Point Digital Signal Processor 352-FCBGA 500mA、具有纹波抑制的LDOamp;micro;MAX封装
500mA, Low-Dropout, Ripple-Rejecting LDO in MAX
From old datasheet system
500mA / Low-Dropout / Ripple-Rejecting LDO in MAX
500mA, Low-Dropout, Ripple-Rejecting LDO in µMAX
|
Maxim Integrated Products, Inc.
MAXIM[Maxim Integrated Products]
MAXIM - Dallas Semiconductor
|
| 1763FS LT1763-2.5 LT1763-1.5 LT1763-1.8 LT1763-3.3 |
500mA, Low Noise, LDO Micropower Regulators(2.5V杈??锛?000mA,浣??澹帮?浣??宸?ǔ???)
500mA, Low Noise, LDO Micropower Regulators(1.5V杈??锛?000mA,浣??澹帮?浣??宸?ǔ???)
500mA, Low Noise, LDO Micropower Regulators(3V杈??锛?000mA,浣??澹帮?浣??宸?ǔ???)
500mA, Low Noise, LDO Micropower Regulators(2.5V输出000mA,低噪声，低压差稳压器) 500mA的，低噪声，LDO的微功耗稳压器2.5V的输出，五零零零毫安，低噪声，低压差稳压器）
500mA, Low Noise, LDO Micropower Regulators(3V输出000mA,低噪声，低压差稳压器)
500mA, Low Noise, LDO Micropower Regulators(3.3V输出000mA,低噪声，低压差稳压器)
500mA, Low Noise, LDO Micropower Regulators(1.8V输出000mA,低噪声，低压差稳压器)
500mA, Low Noise, LDO Micropower Regulators(1.5V输出5000mA,低噪声，低压差稳压器)
From old datasheet system
|
Linear Technology, Corp.
Linear Technology Corporation
|
| MAX6456UT MAX6453UT MAX645310 MAX6454UT MAX6455UT |
uP Supervisors with Separate VCC Reset and Manual Reset Outputs
µP Supervisors with Separate VCC Reset and Manual Reset Outputs 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
|
ON Semiconductor
Maxim Integrated Products, Inc.
MAXIM INTEGRATED PRODUCTS INC
Maxim Integrated Produc...
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| MIC523707 MIC5237-3.3BU MIC5237-3.3YU MIC5237-2.5Y |
500mA Low-Dropout Regulator
IC REG LDO 500MA 3.3V TO263 3.3 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
|
Micrel Semiconductor, Inc.
|
|
