| |
|
 |
Motorola
|
| Part No. |
MC100ES6226
|
| OCR Text |
...EL1 clock frequency selects are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the /2 outputs.
(c) Motorola, Inc. 2001
1
MC100ES6226
VCC
Bank A
/1
CLK CLK
/2
... |
| Description |
2.5/3.3V Dlfferentlal LVPECL 1:9 Clock Distribution Buffer and Clock Dlvlder
|
| File Size |
126.51K /
12 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Device Technology, Inc.
|
| Part No. |
9248YG-92GLFT
|
| OCR Text |
...# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-92. the minimum that the cpuclk is enabled (cpu_stop# high puls... |
| Description |
PROC SPECIFIC CLOCK GENERATOR, PDSO48 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
|
| File Size |
557.37K /
16 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Technology, Inc.
|
| Part No. |
ICS9248YF-PPP-T-LF ICS9248YG-50 ICS9248YG-50T
|
| OCR Text |
...# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-50 . the minimum that the cpuclk is enabled (cpu_stop# high pu... |
| Description |
100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 0.209 INCH, SSOP-28
Peripheral IC 外围芯片
|
| File Size |
307.70K /
11 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Technology, Inc.
|
| Part No. |
ICS9248YG-50LF
|
| OCR Text |
...# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-50 . the minimum that the cpuclk is enabled (cpu_stop# high pu... |
| Description |
100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 6.10 MM, TSSOP-28
|
| File Size |
589.70K /
11 Page |
View
it Online |
Download Datasheet |
| |
|
|
STMicroelectronics N.V.
|
| Part No. |
MT18JDF25672PZ-1G1F1
|
| OCR Text |
...reset: reset# is an active low asychronous input that is connected to each dram and the registering clock driver. after reset# goes high, the dram must be reinitial- ized as though a normal power-up was executed. sx# input chip select: en... |
| Description |
256M X 72 DDR DRAM MODULE, DMA240 HALOGEN FREE, RDIMM-240
|
| File Size |
345.15K /
18 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
