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Fairchild
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Part No. |
74LVTH574 74LVT574
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OCR Text |
...ration of the OE input does not affect the state of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.f... |
Description |
Low Voltage Octal D-Type Flip-Flop From old datasheet system
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File Size |
88.97K /
8 Page |
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ti
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Part No. |
NE556N
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OCR Text |
...itions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation ... |
Description |
IC,TIMER,BIPOLAR,DIP,14PIN,PLASTIC From old datasheet system
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File Size |
85.68K /
6 Page |
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AD[Analog Devices]
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Part No. |
ADE7760 ADE7760ARSRL ADE7760ARS
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OCR Text |
...sign or process change that may affect this parameter.
Rev. 0 | Page 4 of 24
ADE7760 TIMING CHARACTERISTICS
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, TMIN to TMAX = -40C to +85C. Sample tested during in... |
Description |
Single Phase Energy Metering IC with On-Chip Fault Detection and Integrated Oscillator From old datasheet system
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File Size |
380.77K /
24 Page |
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Dallas
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Part No. |
DS21T16 21T16
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OCR Text |
...omponents, the DS21T16 will not affect the SCSI bus during a hot plug operation.
FUNCTIONAL DESCRIPTION
The DS21T16 consists of a bandgap reference, buffer amplifier, and nine termination resistors (Figure 1). The bandgap reference circ... |
Description |
SCSI Terminator From old datasheet system
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File Size |
76.53K /
6 Page |
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ICS
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Part No. |
ICS8432-101
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OCR Text |
...bled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift r... |
Description |
700MHz, Low Phase Noise, LVPECL Frequency Synthesizer From old datasheet system
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File Size |
189.38K /
18 Page |
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ICST[Integrated Circuit Systems]
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Part No. |
ICS8432-11 ICS8432CY-11 ICS8430CY-11T
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OCR Text |
...bled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift r... |
Description |
700MHz / 350MHz, Low Jitter, LVPECL Frequency Synthesizer. (P) From old datasheet system 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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File Size |
175.28K /
16 Page |
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ICS
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Part No. |
ICS84320-01K
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OCR Text |
...bled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift reg... |
Description |
Low Phase Noise, Frequency Synthesizer From old datasheet system
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File Size |
398.24K /
16 Page |
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it Online |
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ICST[Integrated Circuit Systems]
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Part No. |
ICS84321I ICS84321AYI ICS84321AYIT
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OCR Text |
...bled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift r... |
Description |
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER From old datasheet system Low Phase Noise, Frequency Synthesizer. Supports Fibre Channel 1, 2, 10 Gigabit Fibre Channel, Gigabit Ethernet, 10 Gigabit Ethernet, SONET.
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File Size |
287.35K /
16 Page |
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