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  5ns Datasheet PDF File

For 5ns Found Datasheets File :: 9426    Search Time::1.016ms    
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    74LVC16245A 74LVC16245ADGG 74LVC16245ADL 74LVCH16245A

NXP Semiconductors N.V.
Philips Semiconductors
Part No. 74LVC16245A 74LVC16245ADGG 74LVC16245ADL 74LVCH16245A
OCR Text ...ND = 0V; Tamb = 25C; tr = tf 2.5ns SYMBOL tPHL/tPLH CI CI/O CPD PARAMETER Propagation delay An to Bn; Bn to An Input capacitance Input/output capacitance Power dissipation capacitance per buffer VI = GND to VCC1 CL = 50pF VCC = 3.3V CONDIT...
Description 16-bit bus transceiver with direction pin;5V tolerant (3-State)(具有定向引脚5V容限6位总线收发器(三态)) 16位总线收发器引脚方承受5V态)(具有定向引脚的5V的容限的16位总线收发器(三态)
16-bit bus transceiver with direction pin; 5V tolerant 3-State

File Size 83.96K  /  10 Page

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    74LVC16373 74LVC16373A 74LVC16373ADGG 74LVC16373ADL VCH16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL VC16373ADGG

PHILIPS[Philips Semiconductors]
NXP Semiconductors N.V.
Part No. 74LVC16373 74LVC16373A 74LVC16373ADGG 74LVC16373ADL VCH16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL VC16373ADGG VC16373ADL VCH16373ADGG
OCR Text ...ND = 0V; Tamb = 25C; tr = tf 2.5ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay Dn to Qn LE to Qn Input capacitance Power dissipation capacitance per latch VCC = 3.3V CL = 50pF VCC = 3.3V CONDITIONS TYPICAL 3.0 3.4 5.0 26 UNIT ns pF...
Description 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs 3-State LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48

File Size 83.84K  /  10 Page

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    74LVC16374A 74LVC16374ADGG 74LVC16374ADL 74LVCH16374A 74LVCH16374ADGG 74LVCH16374ADL 74LVC_H16374A_4 VCH16374ADL VC16374

PHILIPS[Philips Semiconductors]
NXP Semiconductors N.V.
Part No. 74LVC16374A 74LVC16374ADGG 74LVC16374ADL 74LVCH16374A 74LVCH16374ADGG 74LVCH16374ADL 74LVC_H16374A_4 VCH16374ADL VC16374ADGG VC16374ADL VCH16374ADGG
OCR Text ...ERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN tPHL tPLH tPZH tPZL tPHZ tPLZ tW tsu th fmax Propagation delay CP to Qn 3-State output enable time OE to Qn ...
Description 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs (3-State)
From old datasheet system
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48

File Size 82.15K  /  10 Page

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    74LVC163 74LVC163D 74LVC163DB 74LVC163PW 74LVC163PWDH 74LVC163_2

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74LVC163 74LVC163D 74LVC163DB 74LVC163PW 74LVC163PWDH 74LVC163_2
OCR Text ...ND = 0V; Tamb = 25C; TR = TF 2.5ns SYMBOL PARAMETER Propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS CL = 50 pF VCC = 3.3V TYPICAL 4.9 5...
Description From old datasheet system
Presettable synchronous 4-bit binary counter; synchronous reset

File Size 115.98K  /  12 Page

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    74LVC240 74LVC240A 74LVC240AD 74LVC240ADB 74LVC240APW 7LVC240APWDH

PHILIPS[Philips Semiconductors]
NXP Semiconductors
Part No. 74LVC240 74LVC240A 74LVC240AD 74LVC240ADB 74LVC240APW 7LVC240APWDH
OCR Text ...ERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER Propagation delay 1An to 1Yn; 2An to 2Yn 3-State output enable time 1OE to 1Yn; 2OE to 2Yn 3-State output disable time 1OE to 1Yn; 2OE to...
Description inverting (3-State)
Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting 3-State

File Size 96.42K  /  11 Page

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    74LVC273 74LVC273D 74LVC273DB 74LVC273PW 74LVC273PWDH 74LVC273_2

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74LVC273 74LVC273D 74LVC273DB 74LVC273PW 74LVC273PWDH 74LVC273_2
OCR Text ...ERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL tPHL tPLH tPHL tW tW trem tsu th fmax PARAMETER Propagation delay CP to Qn Propagation delay MR to Qn Clock pulse width HIGH or LOW Master reset pu...
Description From old datasheet system
Octal D-type flip-flop with reset; positive-edge trigger

File Size 95.78K  /  10 Page

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    74LVC374A 74LVC374AD 74LVC374ADB 74LVC374APW 74LVC374A_1 7LVC374APWDH

NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
Part No. 74LVC374A 74LVC374AD 74LVC374ADB 74LVC374APW 74LVC374A_1 7LVC374APWDH
OCR Text ...ND = 0V; Tamb =25C; tr = tf v 2.5ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICA...
Description From old datasheet system
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State
positive edge-trigger (3-State)

File Size 101.32K  /  12 Page

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    74LVC377 74LVC377D 74LVC377DB 74LVC377PW 74LVC377PWDH 74LVC377_2

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74LVC377 74LVC377D 74LVC377DB 74LVC377PW 74LVC377PWDH 74LVC377_2
OCR Text ...ERISTICS GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL tPHL tPLH tW tsu th tsu th fmax PARAMETER Propagation delay CP to Qn Clock pulse width HIGH or LOW Set-up time E to CP Hold time E to CP Set-up tim...
Description From old datasheet system
Octal D-type flip-flop with data enable; positive-edge trigger

File Size 95.61K  /  10 Page

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    74LVC543A 74LVC543AD 74LVC543ADB 74LVC543APW 7LVC543APWDH

NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
Part No. 74LVC543A 74LVC543AD 74LVC543ADB 74LVC543APW 7LVC543APWDH
OCR Text ...ND = 0V; Tamb = 25C; Tr = Tf 2.5ns SYMBOL tPHL/tPLH CI CI/O CPD PARAMETER Propagation delay An to Bn input capacitance input/output capacitance power dissipation capacitance per latch VCC = 3.3V CONDITIONS CL = 50 pF VCC = 3.3V TYPICAL 3.3...
Description Octal D-type registered transceiver 3-State

File Size 104.63K  /  12 Page

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    74LVC573 74LVC573A 74LVC573AD 74LVC573ADB 74LVC573APW LVC573A 7LVC573APWDH

NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
Part No. 74LVC573 74LVC573A 74LVC573AD 74LVC573ADB 74LVC573APW LVC573A 7LVC573APWDH
OCR Text ...ERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th PARAMETER Propagation delay Dn to Qn Propagation delay LE to Qn 3-State output enable time OE to ...
Description Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

File Size 102.69K  /  12 Page

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For 5ns Found Datasheets File :: 9426    Search Time::1.016ms    
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