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Cypress
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| Part No. |
CY7C133 CY7C143 CY7C133-25JC CY7C143-25JC 7C133
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| OCR Text |
...e memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; Chip Enable (CE), Write Enable (R/WUB, R/WLB), and Output Enable (OE). BUSY signals that the port is trying to access the same location currentl... |
| Description |
2K x 16 Dual-Port Static RAM
From old datasheet system
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| File Size |
192.02K /
14 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1342 7C135
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| OCR Text |
...on areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). The ... |
| Description |
4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores
From old datasheet system
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| File Size |
219.32K /
12 Page |
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it Online |
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http://
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
5962-9736101QYA CY7C4271-35AC CY7C4271-15AC CY7C4271-25JC CY7C4271-15JC CY7C4261-15JC CY7C4261-15AC CY7C4271-25AC CY7C4271 CY7C4271-35JI CY7C4261 CY7C4261-10AC CY7C4261-10AI CY7C4261-10JC CY7C4261-10JI CY7C4261-15AI CY7C4261-15JI CY7C4261-25AC CY7C4261-25AI CY7C4261-25JC CY7C4261-25JI CY7C4261-35AC CY7C4261-35AI CY7C4261-35JC CY7C4261-35JI CY7C4271-10AC CY7C4271-10AI CY7C4271-10JC CY7C4271-10JI CY7C4271-15AI CY7C4271-15JI CY7C4271-15LMB CY7C4271-25AI CY7C4271-25JI CY7C4271-35AI CY7C4271-35JC CY7C4261-15ACT CY7C4271-15ACT
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| OCR Text |
...ng high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running ... |
| Description |
12K/32K x 9 Deep Sync FIFOs
AC 6C 6#16S SKT PLUG
16K/32K x 9 Deep Sync FIFOs 16K X 9 OTHER FIFO, 15 ns, PQCC32
16K/32K x 9 Deep Sync FIFOs 16K X 9 OTHER FIFO, 20 ns, PQCC32
16K/32K x 9 Deep Sync FIFOs 16K X 9 OTHER FIFO, 10 ns, PQCC32
16K/32K x 9 Deep Sync FIFOs 32K X 9 OTHER FIFO, 20 ns, PQCC32
16K/32K x 9 Deep Sync FIFOs 32K X 9 OTHER FIFO, 15 ns, PQCC32
16K/32K x 9 Deep Sync FIFOs 32K X 9 OTHER FIFO, 10 ns, PQCC32
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| File Size |
276.48K /
18 Page |
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it Online |
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Cypress
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| Part No. |
CY7C057V 7C057V
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| OCR Text |
...on areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. \
Note: 3. CE is LOW when CE0 VIL and CE1 VIH.
CY7C056V CY7C057V
Each port has independent control pins: Ch... |
| Description |
3.3V 16K/32K x 36FLEx36?Asynchronous Dual-Port Static RAM
From old datasheet system
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| File Size |
278.19K /
22 Page |
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it Online |
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Cypress
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| Part No. |
CY7C138 7C138
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| OCR Text |
...on areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two ... |
| Description |
4K x 8/9 Dual-Port Static RAM
From old datasheet system
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| File Size |
276.28K /
15 Page |
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it Online |
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Cypress
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| Part No. |
CY7C4221 CY7C4231 CY7C4251 CY7C4201 7C42X1
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| OCR Text |
...ng high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running ... |
| Description |
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
From old datasheet system
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| File Size |
330.31K /
21 Page |
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it Online |
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