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lvpecl lvds cml Datasheet PDF File

For lvpecl lvds cml Found Datasheets File :: 1051 Search Time::3.031ms
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				ICST[Integrated Circuit Systems]
Part No.	ICS853058AG ICS853058AGT ICS853058
OCR Text	lvpecl/ECL CLOCK MULTIPLEXER FEATURES * High speed 8:1 differential multiplexer * 1 differential 3.3V or 2.5V lvpecl output * 8 selectable...lvds, cml, SSTL * Maximum output frequency: 2.5GHz * Translates any single ended input signal to LVP...
Description	8:1, DIFFERENTIAL-TO-3.3V OR 2.5V lvpecl/ECL CLOCK MULTIPLEXER
File Size	191.36K / 15 Page	View it Online	Download Datasheet

				Maxim Integrated Produc... MAXIM[Maxim Integrated Products] MAXIM - Dallas Semiconductor
Part No.	MAX9376 MAX9376EUB
OCR Text	lvpecl/lvds Dual Translator General Description The MAX9376 is a fully differential, high-speed, lvds/anything-to-lvpecl/lvds dual translator designed for signal rates up to 2GHz. One channel is lvds/anything-to-lvpecl translator and the ...
Description	From old datasheet system lvds/Anything-to-lvpecl/lvds Dual Translator
File Size	148.16K / 7 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB4L52
OCR Text	lvpecl Translator w/ Internal Termination The NB4L52 is a differential Data and Clock D flip-flop with a differential asynchronous Reset. T...lvds logic levels. When Clock transitions from Low to High, Data will be transferred to the differen...
Description	2.5 to 5.5V ECL D-Flip-flop w/Diff Reset & Input Terms From old datasheet system
File Size	66.58K / 8 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NB6L11 NB6L11DTR2 NB6L11D NB6L11DR2 NB6L11DT
OCR Text	lvpecl/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator....lvds. The outputs are 800 mV ECL signals. * Maximum Input Clock Frequency w 6 GHz Typical * Maximum ...
Description	2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL lvpecl/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 6GHz 2.5V/3.3V Multilevel Input to Differential LVNECL/lvpecl 1:2 Clock or Data Fanout Buffer/Transl From old datasheet system
File Size	112.11K / 12 Page	View it Online	Download Datasheet

				on
Part No.	NB6L16
OCR Text	lvpecl/LVNECL Clock or Data Receiver/Driver/Translator Buffer The NB6L16 is a high precision, low power ECL differential clock or data rece...lvds. Outputs are 800 mV ECL signals. The VBB pin, an internally generated voltage supply, is availa...
Description	6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential LVECL Clock or Data Translator/Receiver/Drive From old datasheet system
File Size	112.87K / 12 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NB6L239 NB6L239MN NB6L239MNR2
OCR Text	lvpecl OUT /1/2/4/8, /2/4/8/16 Clock Divider Features http://onsemi.com The NB6L239 is a high-speed, low skew clock divider with two div...lvds/lvpecl/cml/HSTL * Rise/Fall Time 70 ps Typical * < 10 ps Typical Output-to-Output Skew * Ex. 62...
Description	2.5 V / 3.3 V Any Differential Clock IN to Differential lvpecl OUT 1/2/4/8, 2/4/8/16 Clock Divider From old datasheet system 2.5 V / 3.3V Any Differential Clock IN to Differential lvpecl OUT Dual Bank 1/2/4/8 and 2/4/8/16 Div 2.5 V / 3.3 V Any Differential Clock IN to Differential lvpecl OUT ±1/2/4/8, ±2/4/8/16 Clock Divider 2.5 V / 3.3 V Any Differential Clock IN to Differential lvpecl OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider
File Size	90.71K / 12 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NB7L32M NB7L32MMNG NB7L32MMNR2G
OCR Text	...ermination resistors and accept lvpecl (Positive ECL), cml, or lvds. The high frequency reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of...
Description	2.5V/3.3V, 14GHz 梅2 Clock Divider w/cml Output and Internal Termination(w/cml杈??????ㄧ?绔??2.5V/3.3V, 14GHz 梅2?堕?????? 2.5V/3.3V, 14GHz ÷2 Clock Divider w/cml Output and Internal Termination(w/cml输出和内部终端，2.5V/3.3V, 14GHz ÷2时钟分频 From old datasheet system 2.5V/3.3V, 14GHz ±2 Clock Divider w/cml Output and Internal Termination
File Size	171.32K / 11 Page	View it Online	Download Datasheet

				MICREL[Micrel Semiconductor]
Part No.	SY89112U SY89113UMGTR SY89113U SY89113UMG
OCR Text	...uding 3.3V logic), single-ended lvpecl, differential (AC- or DC-coupled) lvds, HSTL, cml, and lvpecl logic levels as small as 200mV (400mVPP). CLK1 input requires external termination. lvds output swing 325mV into 100 with extremely fast ri...
Description	2.5V Low Jitter, Low Skew 1:12 lvds Fanout Buffer with 2:1 Input MUX and Intermal Termination From old datasheet system
File Size	620.73K / 14 Page	View it Online	Download Datasheet

				ICS
Part No.	ICS8522
OCR Text	...table differential CLK, nCLK or lvpecl clock inputs * CLK, nCLK pair can accept the following differential input levels: lvds, lvpecl, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: lvpecl, cml, SSTL * Maximum output f...
Description	Dual, 1-to-1, LVCMOS-to-LVHSTL Translator. VOHmax = 1.2V From old datasheet system
File Size	93.15K / 12 Page	View it Online	Download Datasheet

For lvpecl lvds cml Found Datasheets File :: 1051 Search Time::3.031ms
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