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Integrated Device Techn...
Integrated Device Technology, Inc.
IDT
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| Part No. |
IDT7284L15 IDT7282L15PAI IDT7281L12 IDT7280L12 IDT7282L20PA IDT7282L20PA8 IDT7285L20PA IDT7285L20PA8 IDT7280L20PA IDT7280L20PA8 IDT7281L15PA8 IDT7284L12PA8 IDT7281L20PA8 IDT7280L15PA8 IDT7283L15PA8 IDT7280L12PA8 IDT7282L12PA8 IDT7283L12PA8 IDT7284L15PA8 IDT7281L12PA8 IDT7282L15PA8 IDT7283L20PA8 IDT7284L15PAI IDT7285L15PAI IDT7280L15PAI IDT7281L15PAI IDT7283L15PAI IDT7281L15PAI8 IDT7284L15PAI8
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| OCR Text |
... ? ? ? ? ? status flags: empty, half-full, full ? ? ? ? ? auto-retransmit capability ? ? ? ? ? high-performance cmos technology ? ? ? ? ? sp...array to allow for control and parity bits at the user?s option. this feature is especially useful ... |
| Description |
ACB 5C 2#8 3#12 PIN PLUG
CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9,DUAL 1,024 x 9, DUAL 2,048 x 9,DUAL 4,096 x 9, DUAL 8,192 x 9 1K X 9 BI-DIRECTIONAL FIFO, 15 ns, PDSO56
CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9,DUAL 1,024 x 9, DUAL 2,048 x 9,DUAL 4,096 x 9, DUAL 8,192 x 9 CMOS双异步FIFO256 × 9，双512 × 9，双1,024 × 9，双2,048 × 9，双4,096 × 9，双8,192 × 9
CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9,DUAL 1,024 x 9, DUAL 2,048 x 9,DUAL 4,096 x 9, DUAL 8,192 x 9 CMOS双异步FIFO56 × 9，双512 × 9，双1,024 × 9，双2,048 × 9，双4,096 × 9，双8,192 × 9
1K x 9 DualAsync FIFO, 5.0V
8K x 9 DualAsync FIFO, 5.0V
256 x 9 DualAsync FIFO, 5.0V
512 x 9 DualAsync FIFO, 5.0V
4K x 9 DualAsync FIFO, 5.0V
2K x 9 DualAsync FIFO, 5.0V
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| File Size |
152.50K /
12 Page |
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Samsung Electronic
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| Part No. |
K9F1208D0B K9F1208B0B K9F1208U0
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| OCR Text |
... i/0 7 v cc/ v ccq v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 128k pages (=4,096 blocks) 512 byte...array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 c... |
| Description |
64M x 8 Bit NAND Flash Memory
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| File Size |
1,022.85K /
45 Page |
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it Online |
Download Datasheet |
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QUICKLOGIC CORP
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| Part No. |
QL3004E-0PL84C
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| OCR Text |
...opagation delays (ns) loads per half column a a. the array distributed networks consist of 24 half columns and the global distributed networks consist of 28 half columns, each driven by an independent buffer. the number of half columns ... |
| Description |
FPGA, 96 CLBS, 4000 GATES, PQCC84
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| File Size |
131.64K /
17 Page |
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it Online |
Download Datasheet |
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Samsung Electronics Inc
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| Part No. |
K9F5608U0A-YIB0 K9F5608U0A-YCB0
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| OCR Text |
...4K Pages (=2,048 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Byte 1 Block = 528 By...array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 ce... |
| Description |
EEPROM,NAND FLASH,33MX8,CMOS,TSSOP,48PIN,PLASTIC
From old datasheet system
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| File Size |
260.49K /
29 Page |
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it Online |
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SGS Thomson Microelectronics
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| Part No. |
AN1120
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| OCR Text |
...d with the m34c02 by making one half of the memory array permanently lockable. this means that after programming the spd data in the dimm, the manufacturer can issue an irreversible command to write-protect this area, still leaving the othe... |
| Description |
EEPROM-BASED APPLICATION SPECIFIC MEMORIES
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| File Size |
51.76K /
7 Page |
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it Online |
Download Datasheet |
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Price and Availability
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