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Cypress
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| Part No. |
CY7C1334F-133AC
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| OCR Text |
...e, during the first clock when emerging from a de selected state, when the device has been deselected. cen 87 input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasser... |
| Description |
2-Mbit (64K x 32) Pipelined SRAM with NoBL(TM) Architecture
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| File Size |
255.08K /
14 Page |
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Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
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| Part No. |
CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350F-100BGI CY7C1350F-100BGC CY7C1350F-225AI CY7C1350F-225BGI CY7C1350F-250BGI CY7C1350F-133AC CY7C1350F-133AI CY7C1350F-133BGC CY7C1350F-133BGI CY7C1350F-166AC CY7C1350F-166AI CY7C1350F-166BGC CY7C1350F-166BGI CY7C1350F-200AC CY7C1350F-200AI CY7C1350F-200BGC CY7C1350F-200BGI CY7C1350F-225AC CY7C1350F-225BGC CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
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| OCR Text |
...ce, during the first clock when emerging from a deselected state, when the device has been deselected. InputSynchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the C... |
| Description |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
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| File Size |
391.04K /
16 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1350 7C1350
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| OCR Text |
...ce, during the first clock when emerging from a deselected state, when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is ma... |
| Description |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构（带总线延迟结构28K × 36至流水线式的SRAM
128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM)
From old datasheet system
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| File Size |
185.89K /
13 Page |
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Cypress
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| Part No. |
CY7C1333F-100AC
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| OCR Text |
...e, during the first clock when emerging from a deselected state, when the device has been deselected. cen 87 input- synchronous clock enable input, active low . when asserted low the clock signal is recog- nized by the sram. when deasse... |
| Description |
2-Mbit (64K x 32) Flow-through SRAM with NoBL(TM) Architecture
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| File Size |
303.00K /
13 Page |
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Broadcom
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| Part No. |
BCM570X
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| OCR Text |
... group, a s well a s the emerging window s server named bu ffers ap i. iscsi is d e signe d to enable end - to-end block st orag e netwo r king over tc p/i p gigabit networks. it is a tran sp ort p r oto c o l fo r ... |
| Description |
PCI-X 10/100/1000BASE-T Controller Software Suite Family
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| File Size |
460.14K /
7 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1346 7C1346
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| OCR Text |
...irst clock of a read cycle when emerging from a deselected state.
Functional Description
The CY7C1346 is 3.3V 64K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic.
Log... |
| Description |
64K x 36 Synchronous-Pipelined Cache RAM(64K x 36同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
442.86K /
17 Page |
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Fujitsu Microelectronics
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| Part No. |
1394
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| OCR Text |
...pecific controllers for the key emerging markets. These include digital cameras, DVD, set-top-box, file systems, and video editing.
The first commercially available LSI to be based on the MB8661x core will be designed for DVC application... |
| Description |
IEEE 1394 SERIAL BUS CONTROLLER
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| File Size |
87.65K /
30 Page |
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it Online |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1334-80AC CY7C1334-133AC CY7C1334-50AC
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| OCR Text |
...ce, during the first clock when emerging from a deselected state, and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal i... |
| Description |
x32 Fast Synchronous SRAM X32号，快速同步SRAM
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| File Size |
193.15K /
12 Page |
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it Online |
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