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divide-by-8 Datasheet PDF File

For divide-by-8 Found Datasheets File :: 6561 Search Time::1.594ms
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				ZARLINK[Zarlink Semiconductor Inc]
Part No.	ZL4081 ZL40813 ZL40813DCE ZL40814 ZL40814DCE ZL40818 ZL40818DCE
OCR Text	...scaler Modulus * * * ZL40813 - Divide by 8 ZL40814 - Divide by 16 ZL40818 - Divide by 4 -40C to +85C Description The ZL40813, 14 and 18 are 5V supply, very high speed low power prescalers for professional applications with a fixed m...
Description	13.5GHz Fixed Modulus divide 16 Prescaler 13.5GHz Fixed Modulus Dividers
File Size	332.09K / 15 Page	View it Online	Download Datasheet

				ZETEX[Zetex Semiconductors]
Part No.	ZSCT1555 ZSCT1555D8 ZSCT1555N8 SCT1555
OCR Text	...ng period. Figure 4 indicates a divide by three. Figure 1 Figure 2 shows the timing diagram for this function. During the output high period further trigger pulses are locked out however the circuit can be reset by application of a negat...
Description	PRECISION SINGLE CELL TIMER
File Size	217.57K / 10 Page	View it Online	Download Datasheet

				Fairchild Semiconductor, Corp. FAIRCHILD[Fairchild Semiconductor]
Part No.	DM74LS393M 74LS393 DM74LS393
OCR Text	...age providing the capability of divide-by-256. The DM74LS393 has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals. Features s Dual version of the popula...
Description	Dual 4-Bit Binary Counter 4位二进制计数
File Size	55.79K / 6 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9176-01 ICS9176M-01 AV9176M-01 ICS9176Q-01
OCR Text	...e input frequency in the normal divide-by-1 mode. In this case, the output can go to 120 MHz with a 60 MHz input clock. The maximum rise and fall time of an output is 1ns and each is TTL-compatible with a 40mA symmetric drive. The ICS9176-0...
Description	Low Skew Output Buffer
File Size	377.43K / 8 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9178-03 ICS9178Y-03
OCR Text	...5% and 60 - 170 MHz at 3.3V 5%. Divide ratios assume BCLK is externally fed back to FBCLK. The 2XPCLK series or Thevinen trace terminations ...by the device. 3 ICS9178-03 Absolute Maximum Ratings VDD referenced to GND . . . . . . . . . . ...
Description	245 MHz Clock Generator and Integrated Buffer for PowerPC™
File Size	490.53K / 8 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT79R3041 IDT79R3041-16 IDT79R3041-20 IDT79R3041-25 IDT79R3041-33 IDT79RV3041 IDT79RV3041-16 IDT79RV3041-20 IDT79RV3041-25 IDT79RV3041-33 IDT79R3041-20J IDT79R3041-20J8 IDT79R3041-20PF IDT79R3041-20PF8 IDT79R3041-33J IDT79R3041-33PF IDT79R3041-33PF8 IDT79R3041-33J8 IDT79R3041-25J IDT79R3041-25J8 IDT79R3041-25PF IDT79R3041-25PF8 IDT79R304116J IDT79R304116PF IDT79R304120J IDT79R304120PF IDT79R304125J IDT79R304125PF IDT79R304133J IDT79R304133PF
OCR Text	...em cost -- RISC CPU -- Multiply/divide unit -- Instruction Cache -- Data Cache -- Programmable bus interface -- Programmable port width supp...by dramatically lowering the cost of using the MIPS architecture. The R3041 is designed to achieve m...
Description	32-bit Low-Cost CPU. NOT RECOMMENDED FOR NEW DESIGNS INTEGRATED RISController FOR LOW-COST SYSTEMS INTEGRATED RISController? INTEGRATED RISController⑩ FOR LOW-COST SYSTEMS
File Size	390.32K / 34 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor] CYPRESS SEMICONDUCTOR CORP
Part No.	IMIZ9972BA IMIZ9972BAT IMIZ9972 Z9972
OCR Text	...Inputs. These inputs select the divide ratio at FB_OUT output. See Table 2. VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1. Feedback Clock Input. Connect to FB_OUT...
Description	Output frequency up to 125 MHz 3.3V, 125-MHz, Multi-Output Zero Delay Buffer 3.3V/ 125-MHz/ Multi-Output Zero Delay Buffer
File Size	86.56K / 9 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72130 LC72130M
OCR Text	.........pulse swallower (built-in divide-by-two prescaler) -- AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct division * IF counter -- IFIN: 0.4 to 12 MHz ...........AM/FM IF counter * Reference frequencies -- ...
Description	AM/FM PLL Frequency Synthesizer CMOS LSI From old datasheet system
File Size	303.37K / 22 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72131M LC72131
OCR Text	.........pulse swallower (built-in divide-by-two prescaler) -- AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct division * IF counter -- IFIN: 0.4 to 12 MHz ...........AM/FM IF counter * Reference frequencies -- ...
Description	From old datasheet system CMOS LSI AM/FM PLL Frequency Synthesizer
File Size	402.78K / 23 Page	View it Online	Download Datasheet

				SANYO[Sanyo Semicon Device]
Part No.	LC72133M LC72133V
OCR Text	.........pulse swallower (built-in divide-by-two prescaler), VDD 2.7 V 10 to 130 MHz ..........pulse swallower (built-in divide-by-two prescaler), VDD 3.0 V -- AMIN: 2 to 40 MHz ..............pulse swallower 0.5 to 10 MHz ...........direct d...
Description	PLL Frequency Synthesizer for Electronic Tuning
File Size	299.12K / 22 Page	View it Online	Download Datasheet

For divide-by-8 Found Datasheets File :: 6561 Search Time::1.594ms
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