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ICS
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| Part No. |
ICS87366
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| OCR Text |
...t levels: LVPECL, LVDS, LVHSTL, hcsl, SSTL * Output frequency: FEC_SEL = 0, 159.375MHz FEC_SEL = 1, 164.355MHz * Cycle-to-cycle jitter: FEC_...lvttl interface levels. Core supply pin. Analog supply pin. Pullup/ Inver ting differential clock in... |
| Description |
1-to-6, Differential to 3.3V LVPECL Clock Generator
From old datasheet system
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| File Size |
83.49K /
10 Page |
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it Online |
Download Datasheet
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ICS
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| Part No. |
ICS8432-101
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| OCR Text |
...ls: LVPECL, LVDS, LVHSTL, SSTL, hcsl * CLK, nCLK or TEST_CLK maximum input frequency: 40MHz * Output frequency range: 25MHz to 700MHz * VCO ...lvttl input levels and translates them to 3.3V LVPECL levels. The CLK, nCLK pair can accept most sta... |
| Description |
700MHz, Low Phase Noise, LVPECL Frequency Synthesizer
From old datasheet system
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| File Size |
189.38K /
18 Page |
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it Online |
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ICS
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| Part No. |
ICS87004I ICS87004
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| OCR Text |
...t levels: LVPECL, LVDS, LVHSTL, hcsl, SSTL * Internal bias on nCLK0 and nCLK1 to support LVCMOS/lvttl levels on CLK0 and CLK1 inputs * Output frequency range: 15.625MHz to 250MHz * Input frequency range: 15.625MHz to 250MHz * VCO range: 250... |
| Description |
Low Skew, Low Jitter, 1-to-4, Clock Generator/Zero Delay Buffer. This device can also be set to multiply or divide by 1, 2, 4, 8.
From old datasheet system
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| File Size |
164.27K /
14 Page |
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it Online |
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ICS
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| Part No. |
ICS87008I
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| OCR Text |
...ls: LVPECL, LVDS, LVHSTL, SSTL, hcsl * CLK0 supports the following input types: LVCMOS, lvttl * Maximum output frequency: 250MHz * Independent bank control for /1 or /2 operation * Glitchless, asynchronous clock enable/disable * Output skew... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator. Industrial Temperature. (P)
From old datasheet system
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| File Size |
203.48K /
15 Page |
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it Online |
Download Datasheet |
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