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Microchip Technology Inc.
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| Part No. |
DV103001 DV103002 DV103003
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| OCR Text |
...formance, low-cost solution for emerging rfid tag applications. with the lowest power consumption, longest read range, highest data rate and fastest anti-collision in the industry, micro id 13.56 mhz devices enable emerging applications su... |
| Description |
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198.81K /
2 Page |
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IBM Microeletronics
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| Part No. |
MPEGCS24D
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| OCR Text |
...ting, broadcast, and a range of emerging applications. ibm mpegcs24 and ibm mpegcs24d decoders can decode mpeg-2 4:2:2 profile at main level video, main profile at main level (mp @ ml) video, and mpeg-2 stereo layer i & ii (cd quality) audi... |
| Description |
Digital Audio/Video Decoders(数字音频/视频译码
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| File Size |
149.38K /
2 Page |
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IBM Microeletronics
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| Part No. |
MPEGCS22
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...hanced features to meet rapidly emerging demand of broadcast, small office/home office (soho), desktop publishing, video post- processing, and profes- sional editing user applications. mpegcs22 this audio/video (a/v) decoder is part of a fa... |
| Description |
MPEG-2 Digital Audio/Video Decoder(MPEG-2系列数字音频/视频译码
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80.54K /
2 Page |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1347F-166AC CY7C1347F-166AI CY7C1347F-166BGC CY7C1347F-166BGI CY7C1347F-166BZC CY7C1347F-250BGC CY7C1347F-133BZC CY7C1347F-133BGI CY7C1347F-200BGC
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...rst clock of a read cycle when emerging from a deselected state. note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. logic block diagram address register... |
| Description |
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 4 ns, PBGA165
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 4 ns, PBGA119
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 3.5 ns, PBGA119
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 3.5 ns, PQFP100
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 2.8 ns, PBGA119
4-Mbit (128K x 36) Pipelined Sync SRAM 4兆位28K的36）流水线同步静态存储器
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| File Size |
424.20K /
19 Page |
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Cypress
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| Part No. |
CY7C1354V25 CY7C1356V25 7C1354V
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| OCR Text |
...ce, during the first clock when emerging from a deselected state and when the device has been deselected. InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH th... |
| Description |
256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture
From old datasheet system
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| File Size |
339.06K /
26 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1218H CY7C1218H-133AXI
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...rst clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk , active low . when asserted, it automatically increments th e address in a burst cycle. ad... |
| Description |
1-Mbit (32K x36) Pipelined Sync SRAM
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| File Size |
354.23K /
16 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1231H-133AXI CY7C1231H-133AXC
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...ce, during the first clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted ... |
| Description |
2-Mbit (128K x 18) Flow-Through SRAM with NoBLArchitecture
2-Mbit (128K x 18) Flow-Through SRAM with NoBL??Architecture
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| File Size |
506.25K /
12 Page |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1223H-166AXC CY7C1223H-166AXI CY7C1223H-133AXI CY7C1223H-133AXC
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| OCR Text |
...irst clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on th e rising edge of clk, active low . when asserted, it automatically increments the address in a burst cycle. ads... |
| Description |
2-Mbit (128K x 18) Pipelined DCD Sync SRAM 128K X 18 CACHE SRAM, 4 ns, PQFP100
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| File Size |
680.26K /
16 Page |
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ALSC
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| Part No. |
AS95L2100
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| OCR Text |
...ecially designed to support the emerging IEEE 802.17 Resilient Packet Ring (RPR) standard at various line interface speeds including OC-12, OC-48 and OC-192 for SONET, and 2.5G & 10G for Ethernet and PacketPHY. The AS95L2100 family is based... |
| Description |
Resilient Packet Ring Controllers?
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| File Size |
146.99K /
4 Page |
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Price and Availability
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