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Elpida Memory, Inc.
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Part No. |
EBE11UD8AGFA-6E-E EBE11UD8AGFA-4A-E EBE11UD8AGFA-5C-E
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OCR Text |
... 8 ? /cas latency (cl): 3, 4, 5 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? average ref...50h 5.0ns* 1 10 sdram access from clock (tac) -6e 0 1 0 0 0 1 0 1 45h 0.45ns* 1 -5c... |
Description |
1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks) LJT 24C 12#16 12#12 PIN PLUG
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File Size |
199.03K /
23 Page |
View
it Online |
Download Datasheet
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![](images/bg04.gif) |
Elpida Memory, Inc.
|
Part No. |
EBE11UD8AEFA-5C-E EBE11UD8AEFA-4A-E
|
OCR Text |
... 8 ? /cas latency (cl): 3, 4, 5 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? average ref...50h 5.0ns* 1 10 sdram access from clock (tac) -5c 0 1 0 1 0 0 0 0 50h 0.5ns* 1 -4a ... |
Description |
1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks) LJT 5C 5#16 SKT RECP
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File Size |
186.28K /
22 Page |
View
it Online |
Download Datasheet
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![](images/bg04.gif) |
Elpida Memory, Inc.
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Part No. |
EBE11ED8AGFA-6E-E EBE11ED8AGFA-5C-E
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OCR Text |
... 8 ? /cas latency (cl): 3, 4, 5 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? average ref...50h 5.0ns* 1 10 sdram access from clock (tac) -6e 0 1 0 0 0 1 0 1 45h 0.45ns* 1 -5c... |
Description |
1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks) LJT 24C 12#16 12#12 PIN PLUG
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File Size |
200.24K /
23 Page |
View
it Online |
Download Datasheet
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![](images/bg04.gif) |
Elpida Memory, Inc.
|
Part No. |
EBE11ED8AEFA-5C-E
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OCR Text |
... 8 ? /cas latency (cl): 3, 4, 5 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? 7.8 s aver...50h 5.0ns* 1 10 sdram access from clock (tac) -5c 0 1 0 1 0 0 0 0 50h 0.5ns* 1 -4a ... |
Description |
1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
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File Size |
185.99K /
22 Page |
View
it Online |
Download Datasheet
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Samsung Electronic
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Part No. |
M368L3223BT1
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OCR Text |
...te10 : add tcc and tac at cl=2.5 in a0 ( ddr200@cl=2)and a2(ddr266@cl=2). 2. byte 23, bte24 : add tcc and tac at cl=2 in b0 ( ddr26...50h 50h 50h 28 minimum row activate to row active delay(=trrd) 15ns 15ns 15ns 3ch 3ch 3ch 29 minimum... |
Description |
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 Data Sheet
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File Size |
21.40K /
3 Page |
View
it Online |
Download Datasheet
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Price and Availability
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