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  vfbga-56 Datasheet PDF File

For vfbga-56 Found Datasheets File :: 234    Search Time::1.36ms    
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    IDT
Part No. IDTCSPT857_A
OCR Text ...able in 48-pin TSSOP and 56-pin VFBGA packages The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one...
Description 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

File Size 121.50K  /  12 Page

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    Integrated Device Technology, Inc.
Part No. IDTCSPT857DPF IDTCSPT857DPFI IDTCSPT857DPAGI
OCR Text ...sop, 40-pin vfqfpn, and 56- pin vfbga packages description: the cspt857d is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y [0:9] , ...
Description 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48

File Size 138.75K  /  15 Page

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    IDT
Part No. CSPT857CBV CSPT857CBV8 CSPT857CBVG8 CSPT857CBVI8 CSPT857CNL CSPT857CNL8 CSPT857CNLG CSPT857CNLG8 CSPT857CPA8 CSPT857CPAG8
OCR Text ...ssop, 40-pin vfqfpn, and 56-pin vfbga packages description: the cspt857c is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y [0:9] , ...
Description 2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver

File Size 136.29K  /  15 Page

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    IDT
Part No. IDTCSPT857C
OCR Text ...d TVSOP, 40-pin MLF, and 56-pin VFBGA packages The CSPT857C is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and on...
Description 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

File Size 135.63K  /  15 Page

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    Integrated Device Technology, Inc.
Part No. IDTCSPT857DPAG
OCR Text ...ssop, 40-pin vfqfpn, and 56-pin vfbga packages description: the cspt857d is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y [0:9] , ...
Description 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER 875 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48

File Size 144.37K  /  15 Page

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    IDT
Part No. CSPT857DBV CSPT857DBV8 CSPT857DBVG8 CSPT857DPAG CSPT857DBVI CSPT857DNL8 CSPT857DPA8 CSPT857DPAG8 CSPT857DBVI8 CSPT857DPAI
OCR Text ...ssop, 40-pin vfqfpn, and 56-pin vfbga packages description: the cspt857d is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y [0:9] , ...
Description 2.5V-2.6V Phase Locked Loop Differential 1:10 SDRAM Clock Driver

File Size 136.36K  /  15 Page

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For vfbga-56 Found Datasheets File :: 234    Search Time::1.36ms    
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