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  sdram-dimm Datasheet PDF File

For sdram-dimm Found Datasheets File :: 3171    Search Time::1.484ms    
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    V437464E24V V437464E24VXTG-10PC V437464E24VXTG-75 V437464E24VXTG-75PC

MOSEL[Mosel Vitelic, Corp]
Part No. V437464E24V V437464E24VXTG-10PC V437464E24VXTG-75 V437464E24VXTG-75PC
OCR Text SDRAM ECC MODULE PRELIMINARY s 168 Pin Registered ECC 67,108,864 x 72 bit Oganization SDRAM Modules s Utilizes High Performance 32M x ...DIMM). The 64M x 72 registered DIMM uses 18 Mosel-Vitelic 32M x 8 ECC SDRAM. The x72 modules are ide...
Description 3.3 VOLT 64M x 72 HIGH PERFORMANCE REGISTERED SDRAM ECC MODULE

File Size 79.38K  /  13 Page

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    V437464Q24V V437464Q24VXTG-10PC V437464Q24VXTG-75 V437464Q24VXTG-75PC

Mosel Vitelic, Corp.
MOSEL[Mosel Vitelic, Corp]
Part No. V437464Q24V V437464Q24VXTG-10PC V437464Q24VXTG-75 V437464Q24VXTG-75PC
OCR Text SDRAM MODULE PRELIMINARY CILETIV LESOM Features Part Number V437464Q24VXTG-75 V437464Q24V Rev. 1.0 January 2002 Description Th...DIMM). The 64M x 72 unbuffered DIMM uses 18 Mosel-Vitelic 64M x 4 ECC SDRAM. The x72 unbuffered modu...
Description 3.3 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE 3.3400 × 72高性能无缓冲ECC内存模块

File Size 87.67K  /  13 Page

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    V437464S24V V437464S24VXTG-10PC V437464S24VXTG-75 V437464S24VXTG-75PC

MOSEL[Mosel Vitelic, Corp]
Part No. V437464S24V V437464S24VXTG-10PC V437464S24VXTG-75 V437464S24VXTG-75PC
OCR Text SDRAM MODULE PRELIMINARY s 168 Pin Unbuffered ECC 67,108,864 x 72 bit Oganization SDRAM Modules s Utilizes High Performance 32M x 8 SD...DIMM). The 64M x 72 unbuffered DIMM uses 18 Mosel-Vitelic 32M x 8 ECC SDRAM. The x72 modules are ide...
Description 3.3 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE

File Size 82.04K  /  12 Page

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    W132

Cypress Semiconductor
Part No. W132
OCR Text ... to meet the needs of new PC133 SDRAM designs, operating to 133 MHz. The W132 was specifically designed to accept SSFTG signals currently be...DIMM applications. The current generation of 256 and 512 megabyte memory modules needs to support 10...
Description Spread Aware/ Ten/Eleven Output Zero Delay Buffer
From old datasheet system
Spread Aware, Ten/Eleven Output Zero Delay Buffer

File Size 102.91K  /  5 Page

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    ICS83840AHT ICS83840AH ICS83840 ICS83840AHLFT ICS83840AHLF

Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
Part No. ICS83840AHT ICS83840AH ICS83840 ICS83840AHLFT ICS83840AHLF
OCR Text SDRAM MUX FEATURES * 40 low skew single-ended DIMM ports * 4 SSTL-2 compatible enable inputs * Maximum Switching Speed: 3ns * Output skew: 120ps (maximum) * Bank skew: 45ps (maximum) * ron = 8 (typical) * Full 2.5V supply modes * 0C to 70...
Description DDR SDRAM MUX

File Size 131.60K  /  8 Page

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    IDT74FCT32932-100 IDT74FCT32932-100PA IDT74FCT32932-100PV IDT74FCT3932-100 IDT74FCT3932-100PA IDT74FCT3932-100PV

Integrated Device Techn...
IDT[Integrated Device Technology]
Integrated Device Technology, Inc.
Part No. IDT74FCT32932-100 IDT74FCT32932-100PA IDT74FCT32932-100PV IDT74FCT3932-100 IDT74FCT3932-100PA IDT74FCT3932-100PV
OCR Text ... SSOP, TSSOP packages Suited to SDRAM applications * * * * * * DESCRIPTION: The FCT3932 uses phase-lock loop technology to lock the f...DIMM Clock, Caches, high speed microprocessors, motherboard clock distribution to DIMMs. FUNCTION...
Description 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

File Size 131.39K  /  9 Page

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    HD74CDCF2509B

HITACHI[Hitachi Semiconductor]
Part No. HD74CDCF2509B
OCR Text ... * Supports PC133 and meets "PC SDRAM registered DIMM specification, Rev. 1.1" Phase-lock loop clock distribution for synchronous DRAM applications External feedback (FBIN) pin is used to synchronize the outputs to the clock input No extern...
Description 140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver
140 MHz, 0 to 85C Operation 3.3-V Phase-lock Loop Clock Driver
140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock Loop Clock Driver

File Size 39.84K  /  11 Page

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    HD74CDCF2510B

HITACHI[Hitachi Semiconductor]
Part No. HD74CDCF2510B
OCR Text ... * Supports PC133 and meets "PC SDRAM registered DIMM specification, Rev. 1.1" Phase-lock loop clock distribution for synchronous DRAM applications External feedback (FBIN) pin is used to synchronize the outputs to the clock input No extern...
Description 140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver
140 MHz, 0 to 85C Operation 3.3-V Phase-lock Loop Clock Driver
140 MHz 0 to 85C Operation 3.3-V Phase-lock Loop Clock Driver
140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock Loop Clock Driver

File Size 42.16K  /  11 Page

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