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Xilinx, Inc.
XILINX INC
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| Part No. |
XCR3064 DS036 XCR3064-12PC68I XCR3064-12PC84I XCR3064-10PC84C
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| OCR Text |
...itecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual cross point switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA a... |
| Description |
EE PLD, 10 ns, PQCC84
EE PLD, 12 ns, PQCC84
64 Macrocell CPLD(64瀹????????缂???昏??ㄤ欢)
EE PLD, 12 ns, PQCC68
From old datasheet system
Product Specification
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| File Size |
111.78K /
15 Page |
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Xilinx
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| Part No. |
XCR3128A DS035
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| OCR Text |
...ion for details). The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, w... |
| Description |
Product Specification
From old datasheet system
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| File Size |
142.39K /
18 Page |
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it Online |
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Xilinx
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| Part No. |
XCR3128 DS034
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| OCR Text |
...itecture. The XPLA architecture consists of logic blocks that are interconnected
MC1 MC2 I/O MC16 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC1 MC2 I/O MC16
MC1 MC2 I/O MC16 16 16 ZIA LOGIC BLOCK 36 36 LOGIC BLOCK 16 16 LOGIC BLOCK... |
| Description |
Product Specification
From old datasheet system
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| File Size |
114.11K /
18 Page |
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it Online |
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Conexant
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| Part No. |
CX74016
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| OCR Text |
... The receive path of the device consists of three Intermediate Frequency (IF) amplifiers with selectable gain, an I/Q demodulator, baseband filters, DC offset compensation circuitry, and selectable gain baseband amplifiers. The transmit pat... |
| Description |
IC,RF MODULATOR/DEMODULATOR,BIPOLAR,LLCC,72PIN,CERAMIC
From old datasheet system
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| File Size |
430.92K /
19 Page |
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it Online |
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LATTICE[Lattice Semiconductor]
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| Part No. |
MACH445-12 MACH445-15 MACH445-15YC MACH445-12YC MACH445-20YC
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| OCR Text |
...ogramming features. The MACH445 consists of eight PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectiv... |
| Description |
High-Density EE CMOS Programmable Logic
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| File Size |
206.54K /
28 Page |
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Cypress
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| Part No. |
CY7C1304V25 7C1304V25
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| OCR Text |
... architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR arc... |
| Description |
9-Mb Pipelined SRAM with QDR?Architecture
From old datasheet system
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| File Size |
215.62K /
23 Page |
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Lattice Semiconductor Corp
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| Part No. |
M4A5-64_32-10JC
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| OCR Text |
...f ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL(R) blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PA... |
| Description |
IC,COMPLEX-EEPLD,64-CELL,10NS PROP DELAY,LDCC,44PIN,PLASTIC
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| File Size |
740.58K /
61 Page |
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it Online |
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Price and Availability
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