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  asychronous Datasheet PDF File

For asychronous Found Datasheets File :: 122    Search Time::2.156ms    
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    Motorola
Part No. MC100ES6222
OCR Text ...B, FSELC, FSELD and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the the /2 outputs. For the functionality of the MR control input, see Figure 5. , "Functional Diagram...
Description Low Voltage 1:15 Dlfferentlal ECL/PECL Clock Dlvlder and Fanout Buffer

File Size 113.56K  /  12 Page

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    ICS9248-55 ICS9248BF-55

ICST[Integrated Circuit Systems]
http://
Part No. ICS9248-55 ICS9248BF-55
OCR Text ... Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-55. The minimum that the CPUCLK is enabled (CPU_STOP# high puls...
Description Pentium/Pro/IITM System Clock Chip 奔腾/专业/ IITM系统时钟芯片
BX Main Clock, Supports 66.6 - 100MHz

File Size 268.23K  /  10 Page

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    ICS952301 ICS952301YG-T

Integrated Circuit Systems
ICS
Part No. ICS952301 ICS952301YG-T
OCR Text ... Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS952301. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse...
Description Frequency Timing Generator for Transmeta Systems

File Size 577.81K  /  12 Page

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    Zarlink
Part No. MT90220
OCR Text ...support MIB Connects to popular asychronous SRAM Provides statistics on the number of HEC errors 8 bit Microprocessor Interface, compatible with Intel and Motorola 3.3V operation / 5V tolerant inputs MQFP-208 pin JTAG Test support * * * ...
Description Octal IMA/UNI PHY Device

File Size 969.43K  /  116 Page

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    IDT
Part No. IDT70121S_L IDT70121L25J IDT70121L35J IDT70121L35JI IDT70125L55J IDT70125L55J8
OCR Text ...typ.) Standby: 1mW (typ.) Fully asychronous operation from either port MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip On-chip port arbitration logic (IDT70121 only) BUSY output flag on Master; BUS...
Description 2K x 9 Dual-Port RAM
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM

File Size 182.41K  /  15 Page

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    A6850

ALTERA[Altera Corporation]
Part No. A6850
OCR Text ...gaCore function implementing an asychronous communications interface adapter (ACIA) Optimized for FLEX(R) and MAX(R) architectures Programmable word lengths, stop bits, and parity Offers divide-by-1, -16, or -64 mode Includes error detectio...
Description Asynchronous Communications Interface ADAPTER(异步通信接口适配

File Size 228.00K  /  15 Page

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    Macronix 旺宏
Part No. MX8325-1 8325_1
OCR Text ...e this chip mostly suitable for asychronous PCI or synchronous PCI design. GENERAL DESCRIPTION There are three PLLs in the MX8325-1 to support smooth transition and glitch-free CPU clock, 24 MHz and PCI bus clock. It can be suited for s...
Description MOTHERBOARD CLOCK GENERATOR
From old datasheet system

File Size 61.79K  /  9 Page

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    ICS
Part No. ICS9148-49
OCR Text ...Timing Diagram CPUS_TOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-49. All other clocks will continue to run while the CPUCLKs clo...
Description BX Main Clock, 2 Chip Clock, Supports 66.6 - 100MHz
From old datasheet system

File Size 360.16K  /  9 Page

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    ICST[Integrated Circuit Systems]
Part No. ICS932S200 ICS932S200YG-T ICS932S200YF-T
OCR Text ...s are held at a Low state. This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0" when driven active(Low). This asynchronous input halts the PCICLK at logic"0" when driven active(Low). PCICLK_F is not affected by this inpu...
Description Frequency Timing Generator for Dual Server/Workstation Systems
From old datasheet system
ServerWorks Champion Le/He CS, Single Ended Outputs

File Size 99.11K  /  12 Page

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For asychronous Found Datasheets File :: 122    Search Time::2.156ms    
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