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Bourns, Inc.
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Part No. |
PPC403GB-KA28C-1
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OCR Text |
...for external bus masters), and refresh rate are user-programma- ble. for each sram/rom bank, the bank size, bank location, number of wait ...1 kb cache is organized as a two-way set associative cache. there are 32 sets of 2 lines, each l... |
Description |
32-Bit Microprocessor 32位微处理
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File Size |
364.34K /
44 Page |
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it Online |
Download Datasheet
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Part No. |
MT45W4MW16PFA-70LIT MT45W4MW16PFA-85IT MT45W4MW16PFA-85LIT
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OCR Text |
...eatures temperature-compensated refresh (tcr) partial-array refresh (par) deep power-down (dpd) mode options designator ?configuration 4 meg x 16 mt45w4mw16p 1 ?package 48-ball vfbga (standard) fa 48-ball vfbga (lead-free) ba 2 ?access time... |
Description |
4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA48 4M X 16 PSEUDO STATIC RAM, 85 ns, PBGA48
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File Size |
450.96K /
34 Page |
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it Online |
Download Datasheet
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Price and Availability
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