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ZARLINK[Zarlink Semiconductor Inc]
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Part No. |
MT9046AN MT9046
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OCR Text |
...he logic level at this input is gated in by the rising edge of F8o. See Table 4. No connection. Leave open circuit Internal Connection. Tie ...Delay Control Circuit Control Signal
Data Sheet
Delay Value
PRI or SEC from Reference Selec... |
Description |
T1/E1 System Synchronizer with Holdover
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File Size |
300.45K /
34 Page |
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it Online |
Download Datasheet
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Intersil
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Part No. |
8406701RA MD82C82B CS82C82
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OCR Text |
.... . . . . . . . . . 35ns Max. * Gated Inputs: - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors * Single 5V Power Supply *...Delay Input to Output Propagation Delay STB to Output Output Disable Time Output Enable Time Input t... |
Description |
CMOS Octal Latching Bus Driver
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File Size |
107.86K /
8 Page |
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it Online |
Download Datasheet
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Zarlink
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Part No. |
ZL30409
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OCR Text |
...he logic level at this input is gated in by the rising edge of F8o. No connection. Leave unconnected Internal Connection. Connect to GND.
...Delay Control Circuit Control Signal
Delay Value
PRI or SEC from Reference Select Mux
Progr... |
Description |
T1/E1 System Synchronizer with Stratum 3 Holdover
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File Size |
277.95K /
32 Page |
View
it Online |
Download Datasheet
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Price and Availability
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