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Zarlink
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| Part No. |
ZL30406
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| OCR Text |
....52 MHz Provides a single-ended cmos clock at 19.44 MHz Provides enable/disable control of output clocks Accepts a cmos reference at 19.44 M...lvpecl differential output clocks at 77.76 MHz, a CML differential clock programmable to 19.44 MHz, ... |
| Description |
SONET/SDH Clock Multiplier PLL
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| File Size |
232.64K /
20 Page |
 View
it Online |
Download Datasheet
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ICS
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| Part No. |
ICS8430-111
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| OCR Text |
...ister Input Output of M divider cmos Fout
FUNCTIONAL DESCRIPTION
The ICS8430-111 features a fully integrated PLL and therefore requires ...lvpecl output buffers. The divider provides a 50% output duty cycle. The programmable features of th... |
| Description |
700MHz, Low Jitter, lvpecl Frequency Synthesizer. (P)
From old datasheet system
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| File Size |
173.06K /
16 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
ZL30414
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| OCR Text |
....52 MHz Provides a single-ended cmos clock at 19.44 MHz Lock Indicator Provides enable/disable control of output clocks Accepts a cmos refer...lvpecl differential output clocks at 622.08 MHz, a CML differential clock at 155.52 MHz and a single... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
220.94K /
23 Page |
View
it Online |
Download Datasheet |
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zarlink
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| Part No. |
ZL30416
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| OCR Text |
....08 MHz Provides a single-ended cmos output clock at 19.44 MHz Accepts a single-ended cmos reference at 19.44 MHz or a differential lvds, lvpecl or CML reference at 19.44 or 77.76 MHz Provides a LOCK indication 8 mm x 8 mm CABGA package 3.3... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
330.43K /
22 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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