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  two-pll Datasheet PDF File

For two-pll Found Datasheets File :: 16314    Search Time::1.906ms    
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    Pericom Technology
PERICOM[Pericom Semiconductor Corporation]
Part No. PI90SD1636AFDE PI90SD1636A PI90SD1636AFC PI90SD1636AFCE PI90SD1636AFD
OCR Text ...ed to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out...PLL Clock Generator RX_CLK<1> RX_CLK<0> 62.5 MHz /2 62.5 MHz 125 MHz RX<9:0> 10 ...
Description SERDES Gigabit Ethernet Transceiver

File Size 329.61K  /  15 Page

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    MOTOROLA[Motorola, Inc]
Part No. MPC9658
OCR Text ... 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The inte...
Description 3.3V 1:10 LVCMOS PLL Clock Generator

File Size 290.07K  /  12 Page

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    P89C557E4 P89C557E4EBB P89C557E4EFB P83C557E4 P83C557E4EBB P83C557E4EFB P80C557E4EFB P80C557E4 P80C557E4EBB P80C557E4EFB

PHILIPS[Philips Semiconductors]
Part No. P89C557E4 P89C557E4EBB P89C557E4EFB P83C557E4 P83C557E4EBB P83C557E4EFB P80C557E4EFB P80C557E4 P80C557E4EBB P80C557E4EFB/01
OCR Text ...andable externally to 64 Kbytes Two standard 16-bit timer/counters An additional 16-bit timer/counter coupled to four capture registers and ...PLL oscillator with 32 kHz reference and software-selectable system clock frequency Seconds Timer So...
Description P83C557E4/P80C557E4/P89C557E4; Single-chip 8-bit microcontroller

File Size 361.76K  /  72 Page

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    MOTOROLA[Motorola, Inc]
Part No. MPC9653
OCR Text ... 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The inte...
Description 3.3V 1:8 LVCMOS PLL CLOCK GENERATOR

File Size 290.68K  /  12 Page

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    Freescale (Motorola)
MOTOROLA[Motorola, Inc]
Part No. MPC962308DT-5HR2 MPC962308 MPC962308D MPC962308D-1 MPC962308D-1H MPC962308D-1HR2 MPC962308D-1R2 MPC962308D-2 MPC962308D-2R2 MPC962308D-3 MPC962308D-3R2 MPC962308D-4 MPC962308D-4R2 MPC962308D-5H MPC962308D-5HR2 MPC962308DT MPC962308DT-1H MPC962308DT-1HR2 MPC962308DT-5H
OCR Text ...w 700 ps max device-device skew Two banks of four outputs, output tristate control by two select inputs Supports a clock I/O frequency range...PLL enters a power down state when there are no rising edges on the REF input. During this state, al...
Description 3.3V 1:8 Zero Delay Buffer
3.3 V Zero Delay Buffer

File Size 403.31K  /  12 Page

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    MOTOROLA[Motorola, Inc]
Part No. MPC961C
OCR Text ...R The MPC961 is offered with two different input configurations. The MPC961C offers an LVCMOS reference clock while the MPC961P offers an...PLL losing lock. The MPC961 is fully 2.5V or 3.3V compatible and requires no external loop filter co...
Description LOW VOLTAGE ZERO DELAY BUFFER

File Size 295.46K  /  12 Page

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    QL8050 QL8150 QL8250 QL8025 QL8325

ETC[ETC]
Part No. QL8050 QL8150 QL8250 QL8025 QL8325
OCR Text ...puts. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from...PLL; internal routing cannot be used for cascading PLLs. PLLs achieve a very short clock-to-out time...
Description LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

File Size 442.48K  /  49 Page

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    TDA8050A TDA8050A_N_1

PHILIPS[Philips Semiconductors]
Part No. TDA8050A TDA8050A_N_1
OCR Text ...I and Q signals. It includes: * Two double balanced mixers * A balanced voltage controlled oscillator (VCO) with 0 to 90 degrees signal generation for modulation * A phase locked loop (PLL) for IF frequency control * A conversion mixer * A ...
Description QPSK transmitter
From old datasheet system

File Size 125.26K  /  28 Page

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For two-pll Found Datasheets File :: 16314    Search Time::1.906ms    
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