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Iterra
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| Part No. |
IT3010
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| OCR Text |
...oupling are allowed. DC-coupled scfl differential input (input HIGH voltage = 0 V, and input LOW voltage = -900 mV) are allowed. Limiting function with 3.8 Vpp differential output 3 dB Bandwidth: 10 GHz Differential gain: 23.5 dB Standard b... |
| Description |
10 GHz medium-gain differential amplifier
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| File Size |
923.77K /
6 Page |
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it Online |
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gigoptix
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| Part No. |
IT3012E
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| OCR Text |
...oupling are allowed. DC-coupled scfl differential input (input "high" voltage = 0 V, input "low" voltage = -900 mV) is allowed. Limiting function with 1.9 Vpp single-ended output 3 dB bandwidth: 8 GHz Single-ended Gain: 17.5 dB Standard bia... |
| Description |
Differential-to-single- ended amplifier
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| File Size |
413.55K /
5 Page |
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it Online |
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OKI[OKI electronic componets]
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| Part No. |
KGL4201
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| OCR Text |
...L) or source-coupled FET logic (scfl). The low-drive disadvantage of DCFL can be improved by using super-buffer FET logic (SBFL). The basic speed of SBFL is slower than DCFL, but SBFL is faster with higher fanouts and longer metal runs. A d... |
| Description |
10-Gbps GaAs Family High-Speed Optical Communications System
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| File Size |
296.16K /
24 Page |
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it Online |
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EUDYNA[Eudyna Devices Inc]
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| Part No. |
F0321818Q
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| OCR Text |
...L) or source coupled FET logic (scfl) circuits are the most popular IC's for high speed digital circuits; the F0321818Q operating under a differential ECL compatible input condition is the best choice as the interface IC to join analog circ... |
| Description |
2 GHz Bandwidth Limiting Amplifier
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| File Size |
114.88K /
11 Page |
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it Online |
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EUDYNA[Eudyna Devices Inc]
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| Part No. |
F0321818M
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| OCR Text |
...L) or source coupled FET logic (scfl) circuits are the most popular IC's for high speed digital circuits; the F0321818M operating under a differential ECL compatible input condition is the best choice as the interface IC to join analog circ... |
| Description |
2 GHz Bandwidth Limiting Amplifier
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| File Size |
476.65K /
10 Page |
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it Online |
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Iterra
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| Part No. |
IT4005D
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| OCR Text |
...nce matching. the it4005d uses scfl i/o levels and allows either single-ended or differential data in put and output. for the clock, a single-ended, dc-coupled input with an internal 50-ohm resistor followed by a dc block is provided. a... |
| Description |
12-Gb/s GaAs MMIC D flip-flop
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| File Size |
1,508.53K /
6 Page |
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it Online |
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EUDYNA[Eudyna Devices Inc]
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| Part No. |
F0321818B
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| OCR Text |
...L) or source coupled FET logic (scfl) circuits are the most popular IC's for high speed digital circuits; the F0321818B operating under a differential ECL compatible input condition is the best choice as the interface IC to join analog circ... |
| Description |
2 GHz Bandwidth Limiting Amplifier
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| File Size |
497.31K /
11 Page |
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it Online |
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Iterra
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| Part No. |
IT4031F
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| OCR Text |
...e dc-coupled. the it4031f uses scfl i/o levels and is designed so to allow for either single ended or differential data input. ultra wideband: up to 12.5 gb/s nrz delay adjustment to 100 ps 900 mvpp single-ended output jitter de... |
| Description |
100-ps wideband phase delay
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| File Size |
551.21K /
5 Page |
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it Online |
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Iterra
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| Part No. |
IT4032D
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| OCR Text |
...terminations. the it4032d uses scfl i/o levels and is designed so to allow for either single ended or differential data input. |
| Description |
50-ps wideband phase delay
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| File Size |
803.43K /
6 Page |
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it Online |
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Iterra
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| Part No. |
IT4033D
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| OCR Text |
... terminations. the it4033d uses scfl i/o levels and is designed so to allow for either single ended or differential data input. |
| Description |
100-ps dual independent wideband phase delay
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| File Size |
419.91K /
5 Page |
View
it Online |
Download Datasheet |
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