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Integrated Device Techn...
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| Part No. |
87339AMI-11LFT 87339AGI-11LFT
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| OCR Text |
...iv_selb0 input pulldown selects divide value for bank b outputs as described in table 3. lvcmos / lvttl interface levels. 4 clk input pulldown non-inverting differential clock input. 5 nclk input pullup inverting differential clock input. 6... |
| Description |
Low Skew, Differential-to-3.3V LVPECL Clock Generator
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| File Size |
193.97K /
15 Page |
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it Online |
Download Datasheet
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IDT
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| Part No. |
IDT5V996BBI8
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| OCR Text |
... l h +7t u h m l inverted h m m divide by 2 h m h divide by 4 comments timing unit calculation (t u ) 1/(16 x f nom ) vco frequency range (f nom ) (1) 100 to 225 mhz skew adjustment range (2) max adjustment: 4.375ns ns 157.5 phase degrees 4... |
| Description |
3.3V Programmable Skew PLL Clock Driver Turboclock II Plus
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| File Size |
64.76K /
9 Page |
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it Online |
Download Datasheet |
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Philips
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| Part No. |
SA7026DK
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| OCR Text |
...ler followed by a cmos counter. divide ratios (512 to 65536) allow a minimum phase comparison frequency of 25khz at 2.5 ghz rf. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main ph... |
| Description |
1.3GHz low voltage fractional-N dual synthesizer.
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| File Size |
424.27K /
14 Page |
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it Online |
Download Datasheet |
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Price and Availability
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