| |
|
 |
CYPRESS[Cypress Semiconductor]
|
| Part No. |
CY7C1353 CY7C1353-66AC CY7C1353-40AC CY7C1353-50AC
|
| OCR Text |
...ce, during the first clock when emerging from a deselected state, when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is ma... |
| Description |
256Kx18 Flow-Through SRAM with NoBL Architecture
|
| File Size |
158.83K /
13 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
|
| Part No. |
CY7C1327G-133AXC CY7C1327G-133AXI CY7C1327G-133BGC CY7C1327G-133BGI CY7C1327G-133BGXC CY7C1327G-133BGXI CY7C1327G-166AXC CY7C1327G-166AXI CY7C1327G-166BGC CY7C1327G-166BGI CY7C1327G-166BGXC CY7C1327G-166BGXI CY7C1327G-200AXC CY7C1327G-200AXI CY7C1327G-200BGC CY7C1327G-200BGI CY7C1327G-200BGXC CY7C1327G-200BGXI CY7C1327G-250BGXI CY7C1327G06 CY7C1327G-250BGC CY7C1327G-250BGXC
|
| OCR Text |
...irst clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. InputAddress St... |
| Description |
4-Mbit (256K x 18) Pipelined Sync SRAM 256K X 18 CACHE SRAM, 2.8 ns, PBGA119
4-Mbit (256K x 18) Pipelined Sync SRAM 256K X 18 CACHE SRAM, 2.6 ns, PBGA119
4-Mbit (256K x 18) Pipelined Sync SRAM 256K X 18 CACHE SRAM, 3.5 ns, PBGA119
4-Mbit (256K x 18) Pipelined Sync SRAM(4-Mb (256K x 18)管道式同步SRAM)
|
| File Size |
369.85K /
18 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
