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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1347G-200AXC CY7C1347G-200AXI CY7C1347G-166AXC CY7C1347G-166AXI CY7C1347G-250AXC CY7C1347G-250AXI CY7C1347G-250BZXI CY7C1347G-250BGXI CY7C1347G-250BZI CY7C1347G-250BGC CY7C1347G-250BGI CY7C1347G-250BZC CY7C1347G-250BGXC CY7C1347G-133BZI CY7C1347G-200BZXI CY7C1347G-166BZXI CY7C1347G-166BZXC
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| OCR Text |
... easy bank selection and output tri-state contro l. in order to provide proper data during depth expansion, oe is masked during the first c...direction of the io pins. when low, the io pins behave as outputs. wh en deasserted high, io pins a... |
| Description |
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 4 ns, PBGA165
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 2.8 ns, PBGA165
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 3.5 ns, PBGA165
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| File Size |
833.02K /
21 Page |
 View
it Online |
Download Datasheet
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1346H-166AXI CY7C1346H-166AXC
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| OCR Text |
... deassert ed high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging...direction of the pins is controlled by oe . when oe is asserted low, the pins behave as out puts. ... |
| Description |
2-Mbit (64K x 36) Pipelined Sync SRAM
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| File Size |
684.87K /
16 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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