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				Zarlink Semiconductor Inc. Zarlink Semiconductor, Inc.
Part No.	SL2610LH2N SL2610IG SL2610LH1Q SL2610LH1N SL2610LH2Q
OCR Text	...ram hi convop ~~ ~ band lo band mid band convopb ifip ifipb ifop ifopb agc bias agc out hi band lo band mid band i 2 c interface port interf...high intermodulation intercept performance so offering high signal to spurious performance in the p...
Description	Wide Dynamic Range Image Reject MOPLL 宽动态范围图像拒MOPLL
File Size	444.24K / 27 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp.
Part No.	CY7B9911-5JCT
OCR Text	....0 ns min max low 15 30 44 22.7 mid 25 50 26 38.5 high 40 100 16 62.5 t u 1 f nom n ----------------------- - = table 2. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1...
Description	Programmable Skew Clock Buffer
File Size	311.71K / 13 Page	View it Online	Download Datasheet

				Maxwell Technologies, Inc
Part No.	7B991
OCR Text	...cc -0.85 -- v three-level input mid voltage (test, fs, xfn) 1 v imm min < v cc < max 1, 2, 3 v cc /2 - 500 mv v cc /2 + 500 mv v thre...high leakage current (ref and fb inputs only) i ih v cc = max, v in = 5v 1, 2, 3 -- 10 a input lo...
Description	Programmable Skew Clock Buffer (PSCB)
File Size	178.52K / 16 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology] Integrated Device Technology, Inc.
Part No.	IDT5V993A IDT5V993-7QI IDT5V993-2Q IDT5V993-2QI IDT5V993-5Q IDT5V993-5QI IDT5V993-7Q IDT5V993A-5QGI8 IDT5V993A-5QI8 IDT5V993A-7QGI IDT5V993A-7QI 5V993A_DATASHEET
OCR Text	... hard-wired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when ...
Description	From old datasheet system 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
File Size	110.26K / 8 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	CY2V995 CY2V995AC CY2V995ACT CY2V995AI CY2V995AIT
OCR Text	...ock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW s...
Description	S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
File Size	279.15K / 10 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC Integrated Device Technology, Inc. IDT[Integrated Device Technology]
Part No.	IDT5V2528 IDT5V2528A IDT5V2528APG IDT5V2528APGG IDT5V2528APGGI IDT5V2528APGI IDT5V2528PG IDT5V2528PGG IDT5V2528PGGI IDT5V2528PGI IDT5V2528APGGI8 IDT5V2528PGGI8 IDT5V2528APGI8
OCR Text	...gnals may be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input. When the G_Ctrl input is mid or high, t...
Description	2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER 2.5V / 3.3V的锁相环时钟驱动器零延迟缓冲 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER .5V / 3.3V的锁相环时钟驱动器零延迟缓冲
File Size	59.21K / 7 Page	View it Online	Download Datasheet

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