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Xilinx, Inc.
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Part No. |
XC2S50E-6PQG208C XC2S300E-6PQG208I
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OCR Text |
...0e ft(g)256 256-ball fine pitch bga xc2s200e fg(g)456 456-ball fine pitch bga xc2s300e fg(g)676 676-ball fine pitch bga xc2s400e xc2s600e no...400 primitives and macros, ranging from 2-input and gates to 16-bit accu- mulators, and includes ari... |
Description |
50,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 384 CLBS, 23000 GATES, 357 MHz, PQFP208 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 1536 CLBS, 93000 GATES, 357 MHz, PQFP208
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File Size |
810.82K /
103 Page |
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it Online |
Download Datasheet |
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Xilinx
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Part No. |
XC2S200E
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OCR Text |
...0e ft(g)256 256-ball fine pitch bga xc2s200e fg(g)456 456-ball fine pitch bga xc2s300e fg(g)676 676-ball fine pitch bga xc2s400e xc2s600e no...400 primitives and macros, ranging from 2-input and gates to 16-bit accu- mulators, and includes ari... |
Description |
(XC2SxxxE) Spartan IIE 1.8V FPGA Family
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File Size |
836.47K /
103 Page |
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it Online |
Download Datasheet |
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MICRON[Micron Technology]
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Part No. |
MT49H8M36 MT49H16M18 MT49H32M9
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OCR Text |
... in total each 32ms) * 144-ball BGA package * HSTL I/O (1.5V or 1.8V nominal) * 25-60 matched impedance outputs * 2.5V VEXT, 1.8V VDD, 1.5V ...400 MHz) 3.3ns (300 MHz) 5ns (200 MHz) * Configuration 8 Meg x 36 16 Meg x 18 32 Meg x 9 * Operating... |
Description |
288Mb CIO Reduced Latency
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File Size |
805.46K /
49 Page |
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it Online |
Download Datasheet |
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Price and Availability
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