| Description |
256 Kbit (32K x 8) nvSrAM; Organization: 32Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 256 Kb; Package: SOICr>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 5; Operating range: 0 to 70 Cr>256K (32K x 8) Static rAM; Density: 256 Kb; Organization: 32Kb x 8; Vcc (V): 4.50 to 5.50 V;r>Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input range: r='#FF0000'>1 MHz to r='#FF0000'>166 MHz; Output range: r='#FF0000'>1 MHz to 200 MHz; Outputs: 6r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): r='#FF0000'>12r>8-r='#FF0000'>mbit (5r='#FF0000'>12K x r='#FF0000'>16) Static rAM; Density: 8 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>16; Vcc (V): 2.20 to 3.60 V;r>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Flow-Through SrAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>r='#FF0000'>18-r='#FF0000'>mbit QDr(TM)-II SrAM 4-Word Burst Architecture; Architecture: QDr-II, 4 Word Burst; Density: r='#FF0000'>18 Mb; Organization: 5r='#FF0000'>12Kb x 36; Vcc (V): r='#FF0000'>1.7 to r='#FF0000'>1.9 Vr>Four Output PCI-X and General Purpose Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to r='#FF0000'>140 MHz; Outputs: 4; Operating range: 0 to 70 Cr>r='#FF0000'>18-r='#FF0000'>mbit QDr(TM)-II SrAM 2-Word Burst Architecture; Architecture: QDr-II, 2 Word Burst; Density: r='#FF0000'>18 Mb; Organization: 5r='#FF0000'>12Kb x 36; Vcc (V): r='#FF0000'>1.7 to r='#FF0000'>1.9 Vr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Flow-Through SrAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>18; Vcc (V): 2.4 to 2.6 Vr>4-r='#FF0000'>mbit (5r='#FF0000'>12K x 8) Static rAM; Density: 4 Mb; Organization: 5r='#FF0000'>12Kb x 8; Vcc (V): 4.50 to 5.50 V;r>4-r='#FF0000'>mbit (256K x r='#FF0000'>16) Static rAM; Density: 4 Mb; Organization: 256Kb x r='#FF0000'>16; Vcc (V): 2.20 to 3.60 V;r>64K x r='#FF0000'>16 Static rAM; Density: r='#FF0000'>1 Mb; Organization: 64Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>r='#FF0000'>1-r='#FF0000'>mbit (64K x r='#FF0000'>16) Static rAM; Density: r='#FF0000'>1 Mb; Organization: 64Kb x r='#FF0000'>16; Vcc (V): 4.5 to 5.5 V;r>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>r='#FF0000'>1-r='#FF0000'>mbit (64K x r='#FF0000'>16) Static rAM; Density: r='#FF0000'>1 Mb; Organization: 64Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>4 r='#FF0000'>mbit (5r='#FF0000'>12K x 8/256K x r='#FF0000'>16) nvSrAM; Organization: 5r='#FF0000'>12Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOPr>4 r='#FF0000'>mbit (5r='#FF0000'>12K x 8/256K x r='#FF0000'>16) nvSrAM; Organization: 256Kb x r='#FF0000'>16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOPr>r='#FF0000'>16-r='#FF0000'>mbit (r='#FF0000'>1M x r='#FF0000'>16 / 2M x 8) Static rAM; Density: r='#FF0000'>16 Mb; Organization: r='#FF0000'>1Mb x r='#FF0000'>16; Vcc (V): 4.50 to 5.50 V;r>4K x r='#FF0000'>16/r='#FF0000'>18 and 8K x r='#FF0000'>16/r='#FF0000'>18 Dual-Port Static rAM with SEM, INT, BUSY; Density: r='#FF0000'>128 Kb; Organization: 8Kb x r='#FF0000'>16; Vcc (V): 4.5 to 5.5 V; Speed: 35 nsr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Flow-Through SrAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 2.4 to 2.6 Vr>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 9 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>8-r='#FF0000'>mbit (5r='#FF0000'>12K x r='#FF0000'>16) Static rAM; Density: 8 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>16; Vcc (V): 4.50 to 5.50 V;r>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Flow-Through SrAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>256K x r='#FF0000'>16 Static rAM; Density: 4 Mb; Organization: 256Kb x r='#FF0000'>16; Vcc (V): 4.5 to 5.5 V;r>9-r='#FF0000'>mbit (256K x 36/5r='#FF0000'>12K x r='#FF0000'>18) Pipelined DCD Sync SrAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>4-r='#FF0000'>mbit (256K x r='#FF0000'>16) Static rAM; Density: 4 Mb; Organization: 256Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>8-r='#FF0000'>mbit (r='#FF0000'>1024K x 8) Static rAM; Density: 8 Mb; Organization: r='#FF0000'>1Mb x 8; Vcc (V): 2.20 to 3.60 V;r>r='#FF0000'>18-r='#FF0000'>mbit (5r='#FF0000'>12K x 36/r='#FF0000'>1M x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: r='#FF0000'>18 Mb; Organization: 5r='#FF0000'>12Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>256K x r='#FF0000'>16 Static rAM; Density: 4 Mb; Organization: 256Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>8-r='#FF0000'>mbit (r='#FF0000'>1M x 8) Static rAM; Density: 8 Mb; Organization: r='#FF0000'>1Mb x 8; Vcc (V): 2.20 to 3.60 V;r>3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 8; Operating range: -40 to 85 Cr>Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: -40 to 85 Cr>r='#FF0000'>18-r='#FF0000'>mbit (5r='#FF0000'>12K x 36/r='#FF0000'>1M x r='#FF0000'>18) Flow-Through SrAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: r='#FF0000'>18 Mb; Organization: 5r='#FF0000'>12Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>r='#FF0000'>18-r='#FF0000'>mbit (5r='#FF0000'>12K x 36/r='#FF0000'>1M x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: r='#FF0000'>18 Mb; Organization: r='#FF0000'>1Mb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>5r='#FF0000'>12K x 8 Static rAM; Density: 4 Mb; Organization: 5r='#FF0000'>12Kb x 8; Vcc (V): 4.5 to 5.5 V;r>r='#FF0000'>18-r='#FF0000'>mbit (5r='#FF0000'>12K x 36/r='#FF0000'>1M x r='#FF0000'>18) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: r='#FF0000'>18 Mb; Organization: 5r='#FF0000'>12Kb x 36; Vcc (V): 2.4 to 2.6 Vr>2.5V or 3.3V, 200-MHz, r='#FF0000'>1:r='#FF0000'>12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: r='#FF0000'>12; Operating range: -40 to 85 Cr>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 5; Operating range: -40 to 85 Cr>2M x 8 Static rAM; Density: r='#FF0000'>16 Mb; Organization: 2Mb x 8; Vcc (V): 3.0 to 3.6 V;r>r='#FF0000'>16 r='#FF0000'>mbit (5r='#FF0000'>12K X 32) Static rAM; Density: r='#FF0000'>16 Mb; Organization: 5r='#FF0000'>12Kb x 32; Vcc (V): 3.0 to 3.6 V;r>3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 8; Operating range: 0 to 70 Cr>8-r='#FF0000'>mbit (r='#FF0000'>1M x 8) Static rAM; Density: 8 Mb; Organization: r='#FF0000'>1Mb x 8; Vcc (V): 3.0 to 3.6 V;r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): r='#FF0000'>125; tPD (ns): 6r>2-r='#FF0000'>mbit (r='#FF0000'>128K x r='#FF0000'>16) Static rAM; Density: 2 Mb; Organization: r='#FF0000'>128Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>r='#FF0000'>16-r='#FF0000'>mbit (r='#FF0000'>1M x r='#FF0000'>16) Static rAM; Density: r='#FF0000'>16 Mb; Organization: r='#FF0000'>1Mb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>4-r='#FF0000'>mbit (256K x r='#FF0000'>18) Pipelined DCD Sync SrAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>5r='#FF0000'>12K (32K x r='#FF0000'>16) Static rAM; Density: 5r='#FF0000'>12 Kb; Organization: 32Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>4-r='#FF0000'>mbit (r='#FF0000'>128K x 36) Pipelined SrAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 4 Mb; Organization: r='#FF0000'>128Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>r='#FF0000'>1M x r='#FF0000'>16 Static rAM; Density: r='#FF0000'>16 Mb; Organization: r='#FF0000'>1Mb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V;r>Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: 0 to 70 Cr>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 9; Operating range: 0 to 70 Cr>MoBL(r) 2 r='#FF0000'>mbit (r='#FF0000'>128K x r='#FF0000'>16) Static rAM; Density: 2 Mb; Organization: r='#FF0000'>128Kb x r='#FF0000'>16; Vcc (V): 2.20 to 3.60 V;r>rambus(r) XDr(TM) Clock Generator; VDD: 2.5 V; Input Frequency: r='#FF0000'>100 MHz to r='#FF0000'>133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: 4r>2-r='#FF0000'>mbit (r='#FF0000'>128K x r='#FF0000'>16) Static rAM; Density: 2 Mb; Organization: r='#FF0000'>128Kb x r='#FF0000'>16; Vcc (V): 2.20 to 3.60 V;r>4-r='#FF0000'>mbit (r='#FF0000'>128K x 36) Pipelined Sync SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: r='#FF0000'>128Kb x 36; Vcc (V): 3.r='#FF0000'>1 to 3.6 Vr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: r='#FF0000'>128; Vcc (V): 5; fMax (MHz): r='#FF0000'>167; tPD (ns): 7r>2.5V or 3.3V, 200-MHz, r='#FF0000'>1:r='#FF0000'>10 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: r='#FF0000'>10; Operating range: 0 to 70 Cr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: r='#FF0000'>128; Vcc (V): 5; fMax (MHz): r='#FF0000'>100; tPD (ns): 7r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: r='#FF0000'>128; Vcc (V): 5; fMax (MHz): r='#FF0000'>125; tPD (ns): 7r>r='#FF0000'>18-r='#FF0000'>mbit DDr-II SrAM 2-Word Burst Architecture; Architecture: DDr-II CIO, 2 Word Burst; Density: r='#FF0000'>18 Mb; Organization: 5r='#FF0000'>12Kb x 36; Vcc (V): r='#FF0000'>1.7 to r='#FF0000'>1.9 Vr>Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: 0 to 70 Cr>Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency range: 25 MHz to r='#FF0000'>100 MHz; Output Frequency range: 25 MHz to r='#FF0000'>100 MHz; Operating range: 0 to 70 C; Package: SOICr>Low Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: 0 to 70 Cr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): r='#FF0000'>143; tPD (ns): 9 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): r='#FF0000'>154; tPD (ns): 6 单芯位CMOS微机r>SINGLE-CHIP 8-BIT CMOS MICrOCOMPUTEr 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): r='#FF0000'>100; tPD (ns): 9 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: r='#FF0000'>128; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): r='#FF0000'>10 单芯位CMOS微机r>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): r='#FF0000'>125; tPD (ns): 6 单芯位CMOS微机r>Three-PLL General-Purpose r='#FF0000'>eprom Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input range: r='#FF0000'>1 MHz to 30 MHz; Output range: .077 MHz to r='#FF0000'>100 MHz; Outputs: 6 单芯位CMOS微机r>8-r='#FF0000'>mbit (5r='#FF0000'>12K x r='#FF0000'>16) MoBL(r) Static rAM; Density: 8 Mb; Organization: 5r='#FF0000'>12Kb x r='#FF0000'>16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机r>High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to r='#FF0000'>1r='#FF0000'>10 MHz; Outputs: 8; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V SDrAM Buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency range: 0 MHz to r='#FF0000'>100 MHz; Outputs: r='#FF0000'>10; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 9; Operating range: -40 to 85 C 单芯位CMOS微机r>Programmable Skew Clock Buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating range: -40 to 85 C 单芯位CMOS微机r>2-r='#FF0000'>mbit (r='#FF0000'>128K x r='#FF0000'>16) Static rAM; Density: 2 Mb; Organization: r='#FF0000'>128Kb x r='#FF0000'>16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机r>MoBL(r) r='#FF0000'>1 r='#FF0000'>mbit (r='#FF0000'>128K x 8) Static rAM; Density: r='#FF0000'>1 Mb; Organization: r='#FF0000'>128Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机r>r='#FF0000'>18-r='#FF0000'>mbit QDr(TM)-II SrAM 2-Word Burst Architecture; Architecture: QDr-II, 2 Word Burst; Density: r='#FF0000'>18 Mb; Organization: r='#FF0000'>1Mb x r='#FF0000'>18; Vcc (V): r='#FF0000'>1.7 to r='#FF0000'>1.9 V 单芯位CMOS微机r>r='#FF0000'>1-r='#FF0000'>mbit (r='#FF0000'>128K x 8) Static rAM; Density: r='#FF0000'>1 Mb; Organization: r='#FF0000'>128Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机r>4-r='#FF0000'>mbit (256K x r='#FF0000'>18) Pipelined Sync SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; Organization: 256Kb x r='#FF0000'>18; Vcc (V): 3.r='#FF0000'>1 to 3.6 V 单芯位CMOS微机r>2-r='#FF0000'>mbit (64K x 32) Pipelined Sync SrAM; Architecture: Standard Sync, Pipeline SCD; Density: 2 Mb; Organization: 64Kb x 32; Vcc (V): 3.r='#FF0000'>1 to 3.6 V 单芯位CMOS微机r>200-MHz Field Programmable Zero Delay Buffer; Voltage (V): 2.5/3.3 V; Frequency range: r='#FF0000'>10 MHz to 200 MHz; Outputs: r='#FF0000'>12; Operating range: -40 to 85 C 单芯位CMOS微机r>2-r='#FF0000'>mbit (r='#FF0000'>128K x r='#FF0000'>16) Static rAM; Density: 2 Mb; Organization: r='#FF0000'>128Kb x r='#FF0000'>16; Vcc (V): 2.20 to 3.60 V; 单芯位CMOS微机r>SINGLE-CHIP 8-BIT CMOS MICrOCOMPUTEr 单芯8位CMOS微机r>2-r='#FF0000'>mbit (256K x 8) Static rAM; Density: 2 Mb; Organization: 256Kb x 8; Vcc (V): 2.20 to 3.60 V; 单芯8位CMOS微机r>Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Output range: 20 MHz to 200 MHz; Outputs: 2 单芯位CMOS微机r>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 5; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 5; Operating range: -40 to 85 C 单芯位CMOS微机r>Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input range: r='#FF0000'>1 MHz to r='#FF0000'>166 MHz; Output range: 0 MHz to 200 MHz; Outputs: 3 单芯位CMOS微机r>r='#FF0000'>1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 350 MHz; Outputs: 8; Operating range: -40 to 85 C 单芯位CMOS微机r>Quad PLL Clock Generator with 2-Wire Serial Interface; Voltage (V): 2.5/3.3 V; Input range: 27 MHz to 27 MHz; Output range: 4.2 MHz to r='#FF0000'>166 MHz; Outputs: 5 单芯位CMOS微机r>2.5V or 3.3V, 200-MHz, r='#FF0000'>1:r='#FF0000'>12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: r='#FF0000'>12; Operating range: 0 to 70 C 单芯位CMOS微机r>3.3V Zero Delay Clock Buffer; Voltage (V): 3.3 V; Frequency range: r='#FF0000'>10 MHz to r='#FF0000'>133 MHz; Outputs: 9; Operating range: 0 to 70 C 单芯位CMOS微机r>High Speed Multi-phase PLL Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 24 MHz to 200 MHz; Outputs: r='#FF0000'>1r='#FF0000'>1; Operating range: 0 to 70 C 单芯位CMOS微机r>2.5V or 3.3V, 200-MHz, r='#FF0000'>1:r='#FF0000'>18 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: r='#FF0000'>18; Operating range: -40 to 85 C 单芯位CMOS微机r>-bit AVr Microcontroller with 8K Bytes In- System Programmable Flash 位AVr微控制器具有8K字节的系统内可编程闪r>2.5V or 3.3V, 200-MHz, r='#FF0000'>1:r='#FF0000'>12 Clock Distribution Buffer; Voltage (V): 2.5/3.3 V; Frequency range: 0 MHz to 200 MHz; Outputs: r='#FF0000'>12; Operating range: 0 to 70 Cr>r='#FF0000'>1:8 Clock Fanout Buffer; Voltage (V): 3.3 V; Frequency range: 0 MHz to 350 MHz; Outputs: 8; Operating range: 0 to 70 Cr>Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency range: 4 MHz to 32 MHz; Output Frequency range: 4 MHz to 32 MHz; Operating range: 0 to 70 C; Package: SOICr>High Speed Low Voltage Programmable Skew Clock Buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to r='#FF0000'>1r='#FF0000'>10 MHz; Outputs: 8; Operating range: 0 to 70 Cr>5V, 3.3V, ISr(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): r='#FF0000'>100; tPD (ns): 9r>
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