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Cypress
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Part No. |
CY7C1393KV18-333BZI CY7C1393KV18-300BZXC
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OCR Text |
...access port phase locked loop (pll) for accurate data placement configurations cy7c1392kv18 ? 2 m 8 cy7c1393kv18 ? 1 m 18 functional description the cy7c1392kv18 and cy7c1393kv18 are 1.8 v synchronous pipelined srams, equipped with ddr ... |
Description |
18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
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File Size |
594.65K /
30 Page |
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it Online |
Download Datasheet
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Microchip
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Part No. |
PL607081UMG
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OCR Text |
...n type pin level pin name 9 pll_bypass i, (se) lvcmos pll bypass, selects output source. 0 = normal pll operation 1 = output from input reference clock or crystal 45 k ? pull-down 3, 11 , 17, 18 , 23, 27, 35 test factory... |
Description |
Clock and Timing - Clock Generation
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File Size |
512.21K /
14 Page |
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it Online |
Download Datasheet
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Microchip
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Part No. |
PL602081UMG PL602081UMG-TR
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OCR Text |
...n type pin level pin name 9 pll_bypass i, (se) lvcmos pll bypass, selects output source. 0 = normal pll operation 1 = output from input reference clock or crystal 45k ? pull down 10 xtal_sel i, (se) lvcmos selects pll input ... |
Description |
Clock and Timing - Clock Generation
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File Size |
794.84K /
15 Page |
View
it Online |
Download Datasheet
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Price and Availability
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