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  flipflop Datasheet PDF File

For flipflop Found Datasheets File :: 385    Search Time::1.453ms    
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    74ACT174 74AC174 74ACT174SJX 74AC174MTC 74AC174SCX 74AC174PC 74AC174MTCX 74AC174SJ 74AC174SJX 74ACT174PC

Fairchild Semiconductor
Part No. 74ACT174 74AC174 74ACT174SJX 74AC174MTC 74AC174SCX 74AC174PC 74AC174MTCX 74AC174SJ 74AC174SJX 74ACT174PC
OCR Text ...ransferred to the corresponding flipflop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for application...
Description Hex D Flip-Flop with Master Reset
From old datasheet system
Hex D-Type Flip-Flop with Master Reset

File Size 98.59K  /  9 Page

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    IDT
Part No. IDT74ALVCH162820
OCR Text flipflop WITH DUAL OUTPUTS IDT74ALVCH162820 FEATURES: * 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, N...
Description 3.3V CMOS 10-BIT flipflop WITH DUAL OUTPUTS

File Size 68.68K  /  6 Page

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    IDT
Part No. IDT74ALVCH162821
OCR Text ... 3.3V CMOS 20-BIT BUS-INTERFACE flipflop WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: * 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R ...
Description 3.3V CMOS 20-BIT BUS-INTERFACE flipflop WITH 3-STATE OUTPUTS AND BUS-HOLD

File Size 74.51K  /  6 Page

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    IDT
Part No. IDT74ALVCH162334
OCR Text ...e A data is stored in the latch/flipflop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVCH162334 has series resistors in the device output structure which will significantly reduce...
Description 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD

File Size 67.67K  /  7 Page

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    SL74HC161 SL74HC161D SL74HC161N HC161

System Logic Semiconductor Co., Ltd.
SLS[System Logic Semiconductor]
Part No. SL74HC161 SL74HC161D SL74HC161N HC161
OCR Text ... and resets the Q output of the flipflop low. Figure 7.Expanded logic diagram SLS System Logic Semiconductor SL74HC161 Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirt...
Description Presettable Counters

File Size 84.48K  /  9 Page

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    IDT
Part No. IDT74FCT2374AT IDT74FCT2374CT
OCR Text ...es Dx CP Qx Qx OE Description D flipflop data inputs Clock Pulse for the register. Enters data on LOW-toHIGH transition 3-State Outputs (TRUE) 3-State Outputs (INVERTED) 3-State Output Enable Input (Active LOW) FUNCTION TABLE(1) Functio...
Description FAST CMOS OCTAL D REGISTER (3-STATE)

File Size 59.38K  /  7 Page

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    XC7336-7 XC7336-10 XC7336-12 XC7336-15 XC7336-5 XC7336

XILINX[Xilinx, Inc]
Xilinx, Inc.
Part No. XC7336-7 XC7336-10 XC7336-12 XC7336-15 XC7336-5 XC7336
OCR Text ...t or Set Input to the Macrocell flipflop. The flip-flop can be configured as a D-type or Toggle flip-flop or transparent for combinatorial outputs. The programmable clock source is one of two global FastCLK signals (FCLK0 or FCLK1) that are...
Description Ultra high-performance EPLD
36-Macrocell CMOS EPLD

File Size 93.28K  /  12 Page

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