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Hynix Semiconductor, Inc.
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| Part No. |
HY5DU56422AT HY5DU56422ALT HY5DU561622AT
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| OCR Text |
...k cke /cs /ras /cas /we address buffer add bank control 16mx4 / bank0 column decoder column address counter sense amp 2-bit prefetch unit ...clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. i... |
| Description |
64Mx4|2.5V|8K|J/M/K/H/L|DDR SDRAM - 256M 64Mx4 |.5V | 8K的|焦九龙/升| DDR SDRAM内存- 256M
16Mx16|2.5V|8K|J/M/K/H/L|DDR SDRAM - 256M 16Mx16显示|.5V | 8K的|焦九龙/升| DDR SDRAM内存- 256M
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| File Size |
361.57K /
36 Page |
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Hitachi,Ltd.
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| Part No. |
HD74CDCV851
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| OCR Text |
buffer for ddr application ade-205-653f (z) rev.6 dec. 2002 description the hd74cdcv851 is a high-performance, low-skew, lo w-jitter, pll clock buffer. it is specifically designed for use with ddr (double data rate) system board applicatio... |
| Description |
Datasheet|ADE-205-653F|DEC.26.02|88K 技术资料| 205 - 653F | DEC.26.02 | 8.8
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| File Size |
88.15K /
16 Page |
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Electronic Theatre Controls, Inc.
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| Part No. |
AMD-640
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| OCR Text |
...sage of the amd-640 chipset i/o buffer behavioral model, which allows a system designer to perform analog simulations of chipset signals tha...clock n t skew is the maximum clock skew between the clock that launches a signal (solid-line clock... |
| Description |
AMD-640 Chipset IBIS I/O Model Application Note AMD640芯片组的IBIS I / O模型应用笔记
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| File Size |
378.30K /
12 Page |
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it Online |
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Xilinx, Inc.
XILINX INC
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| Part No. |
XC4013E-1BG225C XC4010E-2BG225C XC4005E-4PQ100I XC4005E-4PQ160I XC4005E-4PQ100C XC4013E-2BG225I XC4013E-2BG225C XC4010E-3BGG225C XC4003E-2VQG100C XC4010E-2HQ208C
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| OCR Text |
...d junction temperature). global buffer switching characteristic guidelines speed ...clock k t pg xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e 7.0 7.0 7.5 8.0 11.0 11... |
| Description |
13000 GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN FPGA, 576 CLBS, 10000 GATES, 166 MHz, PBGA225
10000 GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN FPGA, 400 CLBS, 7000 GATES, 125 MHz, PBGA225
5000 GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN
FPGA, 100 CLBS, 2000 GATES, 125 MHz, PQFP100
FPGA, 400 CLBS, 7000 GATES, 125 MHz, PQFP208
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| File Size |
68.61K /
17 Page |
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Xilinx, Inc.
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| Part No. |
XA2C128-7CPG132I
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| OCR Text |
...- tions that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. ta b l e ...clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leak... |
| Description |
XA2C128-7CPG132I - NEW PRODUCT FLASH PLD, 7.5 ns, PBGA132
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| File Size |
384.24K /
16 Page |
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Xilinx
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| Part No. |
XCR3032XL
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| OCR Text |
...t min. max. min. max. min. max. buffer delays t in input buffer delay - 0.7 - 1.6 - 2.2 ns t fin fast input buffer delay - 2.2 - 3.0 - 3.1 ns t gck global clock buffer delay - 0.7 - 1.0 - 1.3 ns t out output buffer delay - 1.8 - 2.7 - 3.6 n... |
| Description |
XCR3032XL: 32 Macrocell CPLD
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| File Size |
69.59K /
7 Page |
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it Online |
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