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STMicroelectronics N.V.
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| Part No. |
STSLVDSP27
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| OCR Text |
...ntial line drivers and embedded dpll features sub-low voltage differential signaling: v od = 150mv with r t = 100 , c l = 10pf clock range: 4 to 27 mhz in parallel mode, byp = gnd operative frequency serial mode, byp = v dd ; din... |
| Description |
8-bit low voltage serializer with 1.8V high speed dual differential line drivers and embedded dpll 8位串行的低电压与1.8V高速双差分线路驱动器和嵌入式数字锁相环
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| File Size |
313.92K /
23 Page |
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Infineon
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| Part No. |
SAB82538 SAB8258K
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| OCR Text |
...external clock source * On-chip dpll for clock recovery of each channel * Eight independent baud rate generators * Independent time-slot assignment for each channel with programmable time-slot length (1 - 256 bits) * Async., sync. character... |
| Description |
Enhanced Serial Communication Controller (ESCC8)
From old datasheet system
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| File Size |
16.34K /
2 Page |
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it Online |
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Zarlink
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| Part No. |
ZL30462
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| OCR Text |
...l and Analog Phase Locked Loop (dpll and APLL) technology and can lock to 1 of 2 inputs which can be derived from 2 independent sources. The module has two jitter attenuated output clocks at 19.44MHz (CMOS) and 155.52MHz (LVPECL). In additi... |
| Description |
Timing Module
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| File Size |
172.51K /
20 Page |
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it Online |
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Infineon
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| Part No. |
SAB82532 SAB8253K
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| OCR Text |
...external clock source - On-chip dpll for clock recovery of each channel - Two independent baud rate generators - Independent time-slot assignment for each channel with programmable time-slot length (1 - 256 bits) * Async, sync character ori... |
| Description |
Enhanced Serial Communication Controller (ESCC2)
From old datasheet system
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| File Size |
21.22K /
2 Page |
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it Online |
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Zarlink
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| Part No. |
MT9041B
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.04... |
| Description |
T1/E1 System Synchronizer
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| File Size |
512.83K /
21 Page |
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it Online |
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Infineon
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| Part No. |
PEB2254
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| OCR Text |
...ider /2 /8 PD Divider Osc. RCLK dpll LOS or Master 6 MHz (T1) 8 MHz (XS) 1.5 MHz (T1) 2 MHz (XS) VCO 2 dpll RL(T1) RCLK Alarm Insertion E1 T1 Divider SYNC 16 MHz System Clocks 12 MHz (T1) 16 MHz (E1 Xslicer) SCLKX
Data & Clock Recovery
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| Description |
Frame and Line Interface Component (FALC TM 54)
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| File Size |
31.14K /
3 Page |
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it Online |
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STMicroelectronics N.V.
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| Part No. |
STLC7545
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| OCR Text |
...hase locked loops - separate tx dpll and rx dpll - terminal clock input for tx synchronizationon all multiples of 2400hz (vfast synchronization mode) or on sub-multiple of baud rate (7544 synchronization mode) - bit, baud, sampling and high... |
| Description |
Enhanced V.34 BIS Analog Front-End(单片模拟前端) 国际清算银行增强.34模拟前端（单片模拟前端）
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| File Size |
389.15K /
53 Page |
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it Online |
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Zarlink Semiconductor, Inc.
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| Part No. |
ZL30117
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| OCR Text |
...hz ? digital phase locked-loop (dpll) provides all the features necessary for generating sonet/sdh compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable l... |
| Description |
SONET/SDH OC-48/OC-192 Line Card Synchronizer SONET / SDHOC-48/OC-192线路卡同步器
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| File Size |
380.77K /
24 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT82V3012
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| OCR Text |
...S TRST Fref0 Fref1 IN_sel FLOCK dpll JTAG OSC C32o C19o C19POS C19NEG TIE Control Block
Virtual Reference
Reference Input Switch
C16o C8o C4o C2o C3o C1.5o C6o F0o F8o F16o F19o F32o RSP TSP LOCK
Frequency Select Circuit 0
MON_ou... |
| Description |
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
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| File Size |
358.93K /
30 Page |
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it Online |
Download Datasheet |
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Price and Availability
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