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| Part No. |
UPD45128163G5-A10L-9JF UPD45128163G5-A80-9JF
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| OCR Text |
...organization 4 : x4 8 : x8 memory density 128 : 128m bits synchronous dram nec memory package g5 : tsop (ii) low voltage ...4m words 8 bits 4 banks a0 to a13 note : address inputs dq0 to dq7 : data inputs / outp... |
| Description |
8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
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| File Size |
688.32K /
84 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1514KV18 CY7C1514KV18-300BZXC CY7C1512KV18-300BZXC CY7C1512KV18-300BZC CY7C1514KV18-300BZC CY7C1514KV18-250BZC CY7C1514KV18-250BZI CY7C1514KV18-250BZXC CY7C1514KV18-333BZC CY7C1514KV18-333BZI CY7C1514KV18-333BZXC CY7C1514KV18-333BZXI CY7C1514KV18-250BZXI CY7C1525KV18 CY7C1512KV18-350BZC
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| OCR Text |
... is asserted low available in x8, x9, x18, and x36 configurations full data coherency, providing most current data core v dd = 1.8 v (...4m x 18 cy7c1514kv18 ? 2m x 36 functional description the cy7c1510kv18, cy7c1525kv18, cy7c1512kv18, ... |
| Description |
72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 QDR SRAM, 0.45 ns, PBGA165 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4mb x 18; Vcc (V): 1.7 to 1.9 V 4m X 18 QDR SRAM, 0.45 ns, PBGA165
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| File Size |
603.26K /
33 Page |
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it Online |
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ELPIDA MEMORY INC
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| Part No. |
UPD45128441G5-A10L-9JF UPD45128163G5-A10L-9JF
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| OCR Text |
...organization 4 : x4 8 : x8 memory density 128 : 128m bits synchronous dram nec memory package g5 : tsop (ii) low voltage ...4m words 8 bits 4 banks a0 to a13 note : address inputs dq0 to dq7 : data inputs / outp... |
| Description |
32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
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| File Size |
707.96K /
88 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1543V18-300BZI CY7C1545V18-375BZI
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| OCR Text |
...self-timed writes available in x8, x9, x18, and x36 configurations full data coherency, providing most current data core v dd = 1.8v 0....4m x 18 cy7c1545v18 ? 2m x 36 functional description the cy7c1541v18, cy7c1556v18, cy7c1543v18, and ... |
| Description |
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 4m X 18 QDR SRAM, 0.45 ns, PBGA165 72-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 2M X 36 QDR SRAM, 0.45 ns, PBGA165
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| File Size |
453.24K /
28 Page |
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it Online |
Download Datasheet
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Price and Availability
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