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  differential-to-hstl Datasheet PDF File

For differential-to-hstl Found Datasheets File :: 880    Search Time::1.656ms    
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    INTEGRATED DEVICE TECHNOLOGY INC
Part No. 85211AMI-01LF
OCR Text ...skew, high performance 1-to-2 differential-to-hstl fanout buffer. the clk, nclk pair can accept most standarddifferential input levels.the ics85211i- 01 is characterized to operate from a 3.3v power supply. guaranteed output and part-to...
Description 85211 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

File Size 272.85K  /  14 Page

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    ICS
Part No. ICS8725-01
OCR Text differential-to-hstl ZERO DELAY CLOCK GENERATOR FEATURES * 5 differential HSTL outputs * Selectable differential CLKx, nCLKx input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCS...
Description 1-to-5 HSTL Clock Generator/ Zero Delay Buffer. VOHmax=1.4.
From old datasheet system

File Size 175.74K  /  16 Page

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    ICS
Part No. ICS8725I-01 ICS8725-01I
OCR Text differential-to-hstl ZERO DELAY CLOCK GENERATOR FEATURES * 5 differential HSTL outputs * Selectable differential CLKx, nCLKx input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCS...
Description 1:5 differential-to-hstl Clock Generator
From old datasheet system

File Size 266.68K  /  15 Page

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    Motorola
Part No. MPC9990
OCR Text ...ignal and provides 10 low skew, differential HSTL1 compatible outputs, one HSTL compatible output for system synchronization purposes and on...to 287.5 MHz. The output frequencies are configurable. MPC9990 * * * * * * * * * * * * * Su...
Description Low Voltage PLL Clock Drlver
From old datasheet system

File Size 199.86K  /  12 Page

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    GS81302Q09GE-333I

GSI TECHNOLOGY
Part No. GS81302Q09GE-333I
OCR Text ...single-ended clock inputs, not differential inputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c...
Description 16M X 9 DDR SRAM, 0.45 ns, PBGA165

File Size 414.94K  /  34 Page

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    Cypress
Part No. CY7B9532V
OCR Text ...ernal transmit and receive PLLs Differential CML serial input -- Internal termination and DC-restoration Differential CML serial output -- Source matched for 50 transmission lines Direct interface to standard fiber-optic modules Single +3.3...
Description SONET OC-48 Transceiver
From old datasheet system

File Size 178.35K  /  13 Page

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    HM64YLB36512BP-33 HM64YLB36512BP-28 HM64YLB36512-15

Renesas Electronics Corporation
Part No. HM64YLB36512BP-33 HM64YLB36512BP-28 HM64YLB36512-15
OCR Text ...? sas serves as way select ? differential hstl clock inputs ? late write mode: ? synchronous register to register operation ? differential hstl clock inputs ? register-latch mode: ? synchronous register to latch operation ? d...
Description 512K X 36 LATE-WRITE SRAM, 1.6 ns, PBGA119
16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit)

File Size 370.55K  /  33 Page

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    NB6L239 NB6L239MN NB6L239MNR2

ONSEMI[ON Semiconductor]
Part No. NB6L239 NB6L239MN NB6L239MNR2
OCR Text Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider Features http://onsemi.com The NB6L239 is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/...
Description 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT 1/2/4/8, 2/4/8/16 Clock Divider
From old datasheet system
2.5 V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Dual Bank 1/2/4/8 and 2/4/8/16 Div
2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ±1/2/4/8, ±2/4/8/16 Clock Divider
2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider

File Size 90.71K  /  12 Page

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